• Journal of the Korean School Mathematics Society
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• v.4 no.2
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• pp.135-142
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• 2001

The selected questions for this study was their conversation in problem solving way of working together. To achieve its purpose researcher I chose more detail questions for this study as follows. $\circled1$ What is the difference of strategy according to its level \ulcorner $\circled2$ What is the mathematical ability difference in problem solving process concerning its level \ulcorner This is the result of the study $\circled1$ Difference in the strategy of each class of students. High class-high class students found rules with trial and error strategy, simplified them and restated them in uncertain framed problems, and write a formula with recalling their theorem and definition and solved them. High class-middle class students' knowledge and understanding of the problem, yet middle class students tended to rely on high class students' problem solving ability, using trial and error strategy. However, middle class-middle class students had difficulties in finding rules to solve the problem and relied upon guessing the answers through illogical way instead of using the strategy of writing a formula. $\circled2$ Mathematical ability difference in problem solving process of each class. There was not much difference between high class-high class and high class-middle class, but with middle class-middle class was very distinctive. High class-high class students were quick in understanding and they chose the right strategy to solve the problem High class-middle class students tried to solve the problem based upon the high class students' ideas and were better than middle class-middle class students in calculating ability to solve the problem. High class-high class students took the process of resection to make the answer, but high class-middle class students relied on high class students' guessing to reconsider other ways of problem-solving. Middle class-middle class students made variables, without knowing how to use them, and solved the problem illogically. Also the accuracy was relatively low and they had difficulties in understanding the definition.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.7
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• pp.128-134
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• 2010

In this paper, a high-power 20-way stripline power divider with low insertion loss and low side lobe level is successfully designed, fabricated and measured as a feed network for an S-band linear array antenna having Dolph-Chebyshev current distribution which has a narrow beam width and very low side lobe level (SLL). The 20-way stripline power divider consists of an 8-way power divider, three 4-way power dividers and three ring hybrids. It utilizes a T-junction structure as a basic element for power dividing. Notches and modified input/output N-to-stripline transitions are used for improving insertion loss and return loss. The fabricated power divider shows insertion loss less than 0.3 ㏈ and rms phase mismatch less than 8o in the full bandwidth. A final 40-way power divider is synthesized by combining symmetrically two 20-way power dividers and is expected to have SLL over 40 dB, based on the measured results of the 20-way power divider.

• Journal of electromagnetic engineering and science
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• v.11 no.1
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• pp.16-26
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• 2011

This paper presents high power and high efficiency Doherty amplifiers for 2.345 GHz wireless broadband (WiBro) applications that use a Nitronex 125-W ($P_{3dB}$) GaN high electron mobility transistor (HEMT). Two- and three-way Doherty amplifiers and a saturated Doherty amplifier using Class-F circuitry are implemented. The measured result for a center frequency of 2.345 GHz shows that the two-way Doherty amplifier attains a high $P_{3dB}$ of 51.5 dBm, a gain of 12.5 dB, and a power-added efficiency (PAE) improvement of about 16 % compared to a single class AB amplifier at 6-dB back-off power region from $P_{3dB}$. For a WiBro OFDMA signal, the Doherty amplifier provides an adjacent channel leakage ratio (ACLR) at 4.77 MHz offset that is -33 dBc at an output power of 42 dBm, which is a 9.5 dB back-off power region from $P_{3dB}$. By employing a digital pre-distortion (DPD) technique, the ACLR of the Doherty amplifier is improved from -33 dBc to -48 dBc. The measured result for the same frequency shows that the three-way Doherty amplifier, which has a $P_{3dB}$ of 53.16 dBm and a gain of 10.3 dB, and the saturated Doherty amplifier, which has a $P_{3dB}$ of 51.1 dBm and a gain of 10.3 dB, provide a PAE improvement of 11 % at the 9-dB back-off power region and 7.5 % at the 6-dB back-off region, respectively, compared to the two-way Doherty amplifier.

• Journal of Navigation and Port Research
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• v.26 no.3
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• pp.289-294
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• 2002

The broadband high power 3-way combiner was designed and fabricated for the digital TV repeater. To achieve increase of the bandwidth and the high power capability, Wilkinson type power divider was adopted in our research. First of all, Wilkinson type power divider of equal-split and unequal-split were combined, and the characteristics of the four port in-phase power combiner was simulated for each thickness of dielectric substrates. As the results of simulation, the power combiner fabricated by using dielectric substrate of 120 mil-thickness has the characteristics as follows: insertion loss of less than -651 dB, reflection coefficient of less than -13 dB, isolation among the output ports of less than -15 dB, and pose difference among the output ports of smiler than 13$^{\circ}$. Therefore, this power combiner was possible to improve the limit of microstrip line width due to high impedance, the problem of power loss due to interaction between strip lines in a high power combiner and narrow bandwidth simultaneously. Furthermore, making broadband and high power could be achieved since the fabricated 3-way combiner has good characteristics of insertion loss, the reflection coefficient, separation between ports, and phase difference.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.105-108
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• 2002

Although asynchronous designs have become a promising way to develop complex modern digital systems, there is a few complete design framework for VLSI designers who wish to use automatic CAD tools. Especially, high-level synthesis is not widely concerned until now. In this paper we Proposed a method for high-level synthesis of asynchronous systems as a part of an asynchronous design framework. Our method performs scheduling, allocation, and binding, which are three subtasks of high-level synthesis, in simultaneous using a transformational approach. To deal with complexity of high-level synthesis we use neighborhood search algorithm such as Tabu search.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.9 no.5
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• pp.31-37
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• 2009

In the two-way relay channel, the relay employ Amplify-and-Forward (AF) or Decode-and-Forward (DF) protocol, and broadcast the network-coded signal to both user. In the system, DF protocol provides maximum throughput at low signal to noise ratio(SNR). On the other hand, at high SNR, AF protocol provides maximum throughput. The paper propose active transmission scheme which employ Amplify-and-Forward or Decode-and-Forward protocol based on received SNR at the relay over Two-way relay channel. The optimal threshold is investigated numerically for switching the protocol. Through numerical results, we confirm that the proposed scheme outperforms conventional schemes over two-way relay channel.

• Journal of information and communication convergence engineering
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• v.22 no.1
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• pp.14-22
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• 2024

This study presents the design of a Wilkinson power divider for three-way output ports (WPD3OP), which incorporates a defected ground structure (DGS). An asymmetric power divider is integrated into the output ports of the conventional Wilkinson power divider (WPD), establishing a three-way output port configuration. The DGS introduces periodic or irregular patterns into the ground plane to suppress unwanted electromagnetic wave propagation, and its incorporation can enhance the performance of the power divider, in terms of the power-division ratio, isolation, and bandwidth, by reducing spurious resonances. The proposed design algorithm for an asymmetric power divider for three-way output ports is analyzed via circuit simulations using High-Frequency Simulation Software (HFSS). The results verify the validity of the proposed method. The analysis of the WPD3OP integrated with DGS certifies the achievement of a center frequency of 2 GHz. This confirmation is supported by schematic ideal design simulation results and measurements encompassing insertion losses, return losses, and isolation.

• Journal of Power Electronics
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• v.17 no.2
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• pp.346-357
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• 2017

The Modular Multilevel Converter (MMC) is particularly attractive for medium and high power applications such as High-Voltage Direct Current (HVDC) systems. In order to reach a high voltage, the number of cascaded submodules (SMs) is generally very large. Thus, in the applications with hundreds or even thousands of SMs such as MMC-HVDCs, the sorting algorithm of the conventional voltage balancing strategy is extremely slow. This complicates the controller design and increases the hardware cost tremendously. This paper presents a Two-Way Merge Sort (TWMS) strategy based on the prediction of the capacitor voltages under ideal conditions. It also proposes an innovative Insertion Sort Correction for the TWMS (ISC-TWMS) to solve issues in practical engineering under non-ideal conditions. The proposed sorting methods are combined with the features of the MMC-HVDC control strategy, which significantly accelerates the sorting process and reduces the implementation efforts. In comparison with the commonly used quicksort algorithm, it saves at least two-thirds of the sorting execution time in one arm with 100 SMs, and saves more with a higher number of SMs. A 501-level MMC-HVDC simulation model in PSCAD/EMTDC has been built to verify the validity of the proposed strategies. The fast speed and high efficiency of the algorithms are demonstrated by experiments with a DSP controller (TMS320F28335).

• Proceedings of the Korea Concrete Institute Conference
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• 1999.10a
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• pp.869-881
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• 1999

Inchon International Airport Elevated Road Way is located between the Passenger Terminal Building and Transportaion Center which are Inchon International Airport core construction projects. The deck of the bridge is consists of 5-span or 6-span continuous pre-stressed concrete slab. Steel form has been used to enhance the quality of texture on concrete slab. Steel form has been used to enhance the quality of texture on concrete surface, lower surface of deck slab with the two way arch has been manufactured by highly professional manner in order to get an beautiful exterior architectural looks. The prestressed concrete deck slab is mass concrete structures with a high-specified concrete strength and a varying section in the range of 0.95-2.8m thickness. Therefore high risks of thermal cracking occurrence by heat of hydration highly are expected. To resolve such problem, we adopted type 1 cement and pipe cooking method at construction site through mass concrete specimen test and 3-dimensional analysis. For Pipe cooling we used 25mm diameter stainless pipes with wrinkles. Cooling pipe with spacing 50-60cm has been installed. And continuous pipe cooling with cooling water of 15$^{\circ}C$ was conducted for 2days. In present 8 span of all 29 spans construction has been completed. No thermal cracking heat hydration has been observed yet.

• Journal of Communications and Networks
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• v.18 no.5
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• pp.677-687
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• 2016

Multi-way relay networks (MWRNs) allow multiple users to exchange information with each other through a single relay terminal. MWRNs are often incorporated with capacity achieving lattice codes to enable the benefits of high-rate signal constellations to be extracted. In this paper, we analytically characterize the symbol error rate (SER) performance of a functional decode and forward (FDF) MWRN in the presence of channel estimation errors. Considering M-ary quadrature amplitude modulation (QAM) with square constellations as an important special case of lattice codes, we obtain asymptotic expressions for the average SER for a user in FDF MWRN. The accuracy of the analysis at high signal-to-noise ratio is validated by comparison with the simulation results. The analysis shows that when a user decodes other users with better channel conditions than itself, the decoding user experiences better error performance. The analytical results allow system designers to accurately assess the non-trivial impact of channel estimation errors and the users' channel conditions on the SER performance of a FDF MWRN with M-QAM modulation.