• 제목/요약/키워드: High-order filter

검색결과 789건 처리시간 0.027초

A Novel Log-Domain First-Order Multifunction Filter

  • Kircay, Ali;Cam, Ugur
    • ETRI Journal
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    • 제28권3호
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    • pp.401-404
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    • 2006
  • A new log-domain first-order multifunction filter is proposed in this letter. The proposed filter is systematically derived using the state-space synthesis procedure from a corresponding block diagram. It provides low-pass (LP), high-pass (HP), and all-pass (AP) responses simultaneously for a single input signal. The filter circuit has a very simple structure since it uses only bipolar junction transistors (BJTs) and a grounded capacitor. It can be electronically tuned by changing an external current. The filter has a greater bandwidth due to its inherent current-mode and log-domain operations. PSPICE simulations are given to confirm the theoretical analysis.

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저역통과 LC필터를 가진 전브리지형 인버터로 구동되는 3상유동전동기의 속도제어 시스템에 관한 연구 (A Study on the Speed Control System of a 3 phase Induction Motor driven by the Full Bridge Inverter with a Low Pass LC Filter)

  • 박진길
    • Journal of Advanced Marine Engineering and Technology
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    • 제22권4호
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    • pp.538-550
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    • 1998
  • The variable frequency and variable voltage AC source made by a conventional inverter which is composed of power semi-conductors includes much noises in sine wave due to high frequency switching of DC source. In this paper the 3rd low pass LC filter for a variable speed 3 phase induction motor driven by a full bridge inverter is introduced to solve the EMI problem by serious noise current. The utility of a modified 3rd order Butterworth LC filter is confirmed through FFT analysis of sine waves and noiseless ACsource can be obtained by the proposed LC filter. The speed of a 3 phase induction motor driven by a full bridge inverter with a LC filter is satisfactorily controlled by a digital PID controller under the condition of stepwise load and setpoint changes.

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FPGA를 이용한 심전도 전처리용 적응필터 설계 (Design of FPGA Adaptive Filter for ECG Signal Preprocessing)

  • 한상돈;전대근;이경중;윤형로
    • 대한의용생체공학회:의공학회지
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    • 제22권3호
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    • pp.285-291
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    • 2001
  • In this paper, we designed two preprocessing adaptive filter - high pass filter and notch filter - using FPGA. For minimizing the calculation load of multi-channel and high-resolution ECG system, we utilize FPGA rather than digital signal processing chip. To implement the designed filters in FPGA, we utilize FPGA design tool(Altera corporation, MAX-PLUS II) and CSE database as test data. In order to evaluate the performance in terms of processing time, we compared the designed filters with the digital filters implemented by ADSP21061(Analog Devices). As a result, the filters implemented by FPGA showed better performance than the filters based on ADSP21061. As a consequence of examination, we conclude that FPGA is a useful solution in multi-channel and high-resolution signal processing.

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클러터 환경에 강인한 고속/소형의 접근 표적 탐지/추적 (Robust Detection and Tracking for a High-speed and Small Approaching Target in Clutter)

  • 김지은;노창균;이부환
    • 한국군사과학기술학회지
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    • 제14권4호
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    • pp.676-683
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    • 2011
  • In this paper, we propose a robust method which can detect and track a high-speed small approaching target in a cluttered environment for Korean Active Protection System. The proposed method uses a temporal and spatial filter, tracking filter to detect and track a single target in consecutive order. And it is comprised of a candidate target detection step, a prior target selection step and a target tracking. Field tests on real infrared image sequences show that the proposed method could stably track a high speed and small target in complex background and target occlusion.

$\Delta$ 변환기 후단 처리용 고선형 저전력 연속시간 필터의 설계 (A design of high-linearity low-power contiunous-time filter for post-processing of .SIGMA..DELTA. converters)

  • 홍국태;정현택;손한웅;염왕섭;정강민
    • 한국통신학회논문지
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    • 제22권7호
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    • pp.1579-1589
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    • 1997
  • This paper introduces a monolithic chip 3.3V high-performance continuous-tune filter used in a CDP that can reconstruct the PDM or PWM signal output of a .SIGMA..DELTA. D/A converter. We also mentioned an active RC filter structure and filter order satisfying high-linearity and the design specification. In desigining the OP-AMP, using a structure that accepts some distortion we could reduce the chip area, and reducing the DC path using a new biascircuit gave us better power performance. The designed.SIGMA..DELTA. D/A converter post-processing filter does its smoothering operations and reconstructs the data without reducing the performance of the system.

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임피던스 공진기를 이용한 FR-4 임베디드 광대역필터 (FR-4 Embedded UWB Filter using Uniform Impedance Resonator)

  • 양창수;윤상근;박재영
    • 전기학회논문지
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    • 제56권8호
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    • pp.1471-1475
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    • 2007
  • In this paper, a novel embedded ultra wideband (UWB) band-pass filter is presented on a FR-4 package substrate including high Dk resin coated copper (${\varepsilon}_r=30$) film. The proposed UWB filter is comprised of a parallel resonator with meander-type uniform impedance resonator (UIR) and two series resonators with high Q circular stacked spiral inductor and metal-insulator-metal (MIM) capacitor. In order to obtain excellent attenuation characteristics by generating attenuation poles in lower and upper stop bands, a single MIM capacitor is added to each resonator. The fabricated FR-4 embedded UWB filter has insertion loss of -1.0dB and return loss of -11dB, respectively. It has also extremely wide bandwidth (over 50%) and small size ($3.7{\times}4{\times}0.77\;mm^3$) which is compatible with LTCC devices.

A Dual-Band Through-the-Wall Imaging Radar Receiver Using a Reconfigurable High-Pass Filter

  • Kim, Duksoo;Kim, Byungjoon;Nam, Sangwook
    • Journal of electromagnetic engineering and science
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    • 제16권3호
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    • pp.164-168
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    • 2016
  • A dual-band through-the-wall imaging radar receiver for a frequency-modulated continuous-wave radar system was designed and fabricated. The operating frequency bands of the receiver are S-band (2-4 GHz) and X-band (8-12 GHz). If the target is behind a wall, wall-reflected waves are rejected by a reconfigurable $G_m-C$ high-pass filter. The filter is designed using a high-order admittance synthesis method, and consists of transconductor circuits and capacitors. The cutoff frequency of the filter can be tuned by changing the reference current. The receiver system is fabricated on a printed circuit board using commercial devices. Measurements show 44.3 dB gain and 3.7 dB noise figure for the S-band input, and 58 dB gain and 3.02 dB noise figure for the X-band input. The cutoff frequency of the filter can be tuned from 0.7 MHz to 2.4 MHz.

KSR-III 김발엔진 구동장치 서보필터 설계

  • 선병찬;정호락
    • 항공우주기술
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    • 제1권2호
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    • pp.105-112
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    • 2002
  • 본 논문에서는 KSR-III 김발엔진 구동장치 서보필터 설계 방안에 대한 연구 결과를 정리하였다. 비선형 해석모델에 대한 선형 근사모델을 기준으로 서보필터 설계를 수행하였다. 서보필터의 기본 형상으로서 설계 및 제작의 편의성 관점에서 2차의 Butterworth 저주파 필터를 우선적으로 고려하였다. 저주파 필터만을 사용할 경우 발생하는 불안정성 문제를 해결하기 위해 1차의 보상기를 추가하였다. 전체 로켓 시스템의 위상 안정성 여유와 공진 이득 감쇠를 동시에 고려할 경우, 2차의 Butterworth 필터로는 설계에 한계가 있었으며, 노치 필터를 사용해야 함을 알 수 있었다. 결과적으로, KSR-III 김발엔진 구동장치용 서보필터로는 2차 저주파 노치필터를 궤환신호와 명령신호 간의 오차 신호에 위치시키는 것이 효과적이라는 결론을 얻었다. 여기서 제시한 서보필터 형상을 토대로 추후 KSR-III 비행용 서보필터 제작 및 시험이 이루어질 예정이다.

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CIC 필터를 이용한 저면적 데시메이션 필터 설계 (Design of Low Area Decimation Filters Using CIC Filters)

  • 김선희;오재일;홍대기
    • 반도체디스플레이기술학회지
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    • 제20권3호
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    • pp.71-76
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    • 2021
  • Digital decimation filters are used in various digital signal processing systems using ADCs, including digital communication systems and sensor network systems. When the sampling rate of digital data is reduced, aliasing occurs. So, an anti-aliasing filter is necessary to suppress aliasing before down-sampling the data. Since the anti-aliasing filter has to have a sharp transition band between the passband and the stopband, the order of the filter is very high. However, as the order of the filter increases, the complexity and area of the filter increase, and more power is consumed. Therefore, in this paper, we propose two types of decimation filters, focusing on reducing the area of the hardware. In both cases, the complexity of the circuit is reduced by applying the required down-sampling rate in two times instead of at once. In addition, CIC decimation filters without a multiplier are used as the decimation filter of the first stage. The second stage is implemented using a CIC filter and a down sampler with an anti-aliasing filter, respectively. It is designed with Verilog-HDL and its function and implementation are validated using ModelSim and Quartus, respectively.

연속재생 DPF의 재생 성능에 미치는 차량 운행패턴의 영향 (Influence of Driving Pattern on Regeneration Performance of Continuously Regenerating Diesel Particulate Filter)

  • 황진우;이창식
    • 대한기계학회논문집B
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    • 제33권5호
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    • pp.358-364
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    • 2009
  • This paper is to investigate the influence of driving patterns of slow and high speed vehicles on the performance of continuously regenerating diesel particulate filter(DPF) system matched with operating conditions in field application. The DPF performance test for field application was carried out for two identical DPFs installed to slow and high speed vehicles. A slow speed vehicle was selected among local buses which have driving patterns to repeat running and stop frequently, while a high speed vehicle was prepared to have long route of high speed over 60km/h like inter-city buses. In this test, the regeneration performance on the DPF of slow speed vehicle deteriorated because of high soot load index(SLI) in spite of same balance point temperature(BPT) distribution for high speed vehicle. The DPF of slow speed vehicle melted in the end because the rapid increase of back pressure caused high temperature over $1200^{\circ}C$ in the ceramic wall of DPF. The PM components like ash collected to the filter in the DPF were analyzed in order to investigate the cause of the defect and provide an operation performance of DPF system. In the result of the analysis, high levels of lubrication oil ash(Ca, Mg, P, Zn) were detected.