• Transactions of the Korean Society of Mechanical Engineers A
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• v.29 no.2 s.233
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• pp.333-340
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• 2005

Feedrate is one of the factors that have the significant effects on the productivity, qualify and tool life in the cutting mechanism as well as cutting velocity, depth of cut and width of cut. In this study, in order to realize the high-efficient machining, a new feedrate optimization method is proposed based on the concept that the optimum feedrate can be derived from the allowable cutting power since the cutting power can be predicted from the cutting parameters as feedrate, depth of cut, width of cut, chip thickness, engagement angle, rake angle, specific cutting force and so on. Tool paths are extracted from the original NC program via the reverse post-processing process and converted into the infinitesimal tool paths via the interpolation process. And the novel NC program is reconstructed by optimizing the feedrate of infinitesimal tool paths. Especially, the fast feedrate optimization is realized by using the Boolean operation based on the Goldfeather CSG rendering algorithm, and the simulation results reveal the availability of the proposed optimization method dramatically reducing the cutting time and/or the optimization time. As a result, the proposed optimization method will go far toward improving the productivity and qualify.

• IEIE Transactions on Smart Processing and Computing
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• v.3 no.5
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• pp.267-270
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• 2014

This paper presents the comparative performance of an adaptive FIR filter for a Delayed LMS algorithm. The delayed error signal was used to obtain a Delayed LMS algorithm to allow efficient pipelining for achieving a small critical path and area efficient implementation. This paper presents hardware efficient results (device utilization parameters) and power consumed. The FPGA families (Artix-7, Virtex-7, and Kintex-7) for a low voltage perspective are shown. The synthesis results showed that the artix-7 CMOS family achieves the lowest power consumption of 1.118 mW with 83.18 % device utilization. Different Precision strategies, such as the speed optimization and power optimization, were imposed to achieve these results. The algorithm was implemented using MATLAB (2013b) and synthesized on the Leonardo spectrum.

• Journal of information and communication convergence engineering
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• v.15 no.1
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• pp.21-27
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• 2017

In this research, we study the outage probability for distributed space-time coding-based cooperative (DSTC) systems with amplify-and-forward relaying over Rayleigh fading channels with a high temporal correlation where the direct link between the source and the destination is available. In particular, we derive the upper and lower bounds of the outage probability as well as their corresponding asymptotic expressions. In addition, using only the average channel powers for the source-to-relay and relay-to-destination links, we propose an efficient power allocation scheme between the source and the relay to minimize the asymptotic upper bound of the outage probability. Through a numerical investigation, we verify the analytical expressions as well as the effectiveness of the proposed efficient power allocation. The numerical results show that the lower and upper bounds tightly correspond to the exact outage probability, and the proposed efficient power allocation scheme provides an outage probability similar to that of the optimal power allocation scheme that minimizes the exact outage probability.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.31 no.9
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• pp.960-966
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• 2007

High-efficient machining, which means to machine a part in the least amount of time, is the most effective tool to improve productivity. In this study, a new feed optimization method based on virtual manufacturing was proposed to realize the high-efficient machining in turning process through the cutting power regulation. The cutting area was evaluated by using the Boolean intersection operation between the cutting tool and workpiece. And the cutting force and power were predicted from the cutting parameters such as feed, depth of cut, spindle speed, specific cutting force, and so on. Especially, the reliability of the proposed optimization method was validated by comparing the predicted and measured cutting forces. The simulation results showed that the proposed optimization method could effectively enhance the productivity in turning process.

• ETRI Journal
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• v.33 no.1
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• pp.140-143
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• 2011

Recent test data compression techniques raise concerns regarding power dissipation and compression efficiency. This letter proposes a new test data compression scheme, twin symbol encoding, that supports block division skills that can reduce hardware overhead. Our experimental results show that the proposed technique achieves both a high compression ratio and low-power dissipation. Therefore, the proposed scheme is an attractive solution for efficient test data compression.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.53 no.3
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• pp.180-187
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• 2004

A conventional power supply of a microwave oven has a 60Hz transformer and high voltage capacitor(HVC). Though it is very simple and has low cost, it has several problems such as large size, heavy weight and low efficiency To improve these problems, various high frequency inverter type power supply have been investigated and developed in recent years. But these cost is higher than the conventional one due to additional control circuit, fast switching devces. In this paper, a novel pulse power supply for microwave oven using high frequency transformer embedded HVC(High Voltage Capacitor) is proposed for down-sizing, cost reduction and efficient improvement. To verify the effectiveness of the proposed transformer, an equivalent circuit of transformer embedded HVC is derived and it's characteristic is described. And the validity of the proposed pulse power supply embedded HVC-high frequency transformer is shown by simulations and experiments accroding to various operating conditions.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.101-104
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• 2002

This paper propose that is algorithm of power dissipation reduction in the high level synthesis design for DSP(Digital Signal Processor), as the portable terminal system recently demand high power dissipation. This paper obtain effect of power dissipation reduction and switching activity that increase correlation of operands as input data of function unit. The algorithm search loop or repeatedly data to the input operands of function unit. That can be reduce the power dissipation using the new low power high level synthesis algorithm. In this Paper, scheduling operation search same nodes from input DFG(Data Flow Graph) with correlation coefficient of first input node and among nodes. Function units consist a multiplier, an adder and a register. The power estimation method is added switching activity for each bits of nodes. The power estimation have good efficient using proposed algorithm. This paper result obtain more Power reduction of fifty percents after using a new low power algorithm in a function unit as multiplier.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.499-500
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• 2008

In this paper, we design and implement the monolithic power factor correction IC for system power modules using a high voltage(50V) CMOS process. The power factor correction IC is designed for power applications, such as refrigerator, air-conditioner, etc. It includes low voltage logic, 5V regulator, analog control circuit, high-voltage high current output drivers, and several protection circuits. And also, the designed IC has standby detection function which detects the output power of the converter stage and generates system down signal when load device is under the standby condition. The simulation and experimental results show that the designed IC acts properly as power factor correction IC with efficient protective functions.

• Proceedings of the KIPE Conference
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• 2020.08a
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• pp.91-93
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• 2020

In recently days using distributed power generation systems constructed with boost type dc-dc converters is being extremely popularized because of the rising need of environment friendly energy generation power systems. In this paper a new constructed An efficient Step-Up DC-DC Converter for DC Grid Applications s proposed to boost a low level DC voltage(36-80V) to high DC bus (380V) level. When comparing to other step-up converters, the proposed topology has a reduced number of switching devices, can make high quality power with lower input current ripple and has wider input DC voltage range. Finally, the performance of the proposed topology is presented by simulation results with 350W hardware prototype.

• Proceedings of the KIEE Conference
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• 2002.06a
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• pp.79-82
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• 2002

Non-linear loads are the sources of power systems harmonics, and the power quality is influenced by harmonics, Recently, the requirements of power quality is important. For the power quality problems. it is very important that the development of power measurement circuit for non-linear load. In this paper, it is discoursed on that high speed sampling circuit and efficient power analysis algorithms. The sampling circuit is implemented using FPGA. Since the power measurement circuit system is composed by FPGA and efficient power algorithms. it is practicable application that accurate power measurement, stable protection relaying, and low cost system configuring.