• IEIE Transactions on Smart Processing and Computing
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• v.5 no.1
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• pp.29-34
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• 2016

A controller area network (CAN) controller is an integral part of an electronic control unit, particularly in an advanced driver assistance system application, and its characteristics should always be advantageous in all aspects of functionality especially in real time application. The cost should be low, while maintaining the functionality and reliability of the technology. However, a CAN protocol implementing serial operation results in slow throughput, especially in a cyclical redundancy checking (CRC) unit. In this paper, digital signal processing (DSP) algorithms are implemented, namely pipelining, unfolding, and retiming the CAN controller in the CRC unit, particularly for the encoder and decoder sections. It must attain a feasible iteration bound, a critical path that is appropriate for a CAN system, and must obtain a superior design of a high-speed parallel circuit for the CRC unit in order to have a faster transmission rate. The source code for the encoder and decoder was formulated in the Verilog hardware description language.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.465-472
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• 2017

Security has become one of the most important requirements for various devices for multi-sensor based embedded systems. The AES (Advanced Encryption Standard) algorithm is widely used for security, however, it requires high computing power. In order to reduce the CPU power for the data encryption of images, we propose a new image encryption module using hardware memoization, which can reuse previously generated data. However, as image pixel data are slightly different each other, the reuse rate of the simple memoization system is low. Therefore, we further apply an approximate concept to the memoization system to have a higher reuse rate by sacrificing quality. With the novel technique, the throughput can be highly improved by 23.98% with 14.88% energy savings with image quality loss minimization.

• Journal of Computing Science and Engineering
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• v.11 no.2
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• pp.58-68
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• 2017

While graphics processing units (GPUs) can be used to improve the performance of real-time embedded applications that require high throughput, it is challenging to estimate the worst-case execution time (WCET) of GPU programs, because modern GPUs are designed for improving the average-case performance rather than time predictability. In this paper, a reordering framework is proposed to regulate the access to the GPU data cache, which helps to improve the accuracy of the estimation of GPU L1 data cache miss rate with low performance overhead. Also, with the improved cache miss rate estimation, tighter WCET estimations can be achieved for GPU programs.

• Proceedings of the Korea Information Processing Society Conference
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• 2017.11a
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• pp.163-165
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• 2017

최근 단일 모바일 기기에서 처리하기 어려운 모바일 컴퓨팅을 처리하는 연구가 진행되고 있다. 모바일 기기로 구성된 모바일 클라우드내에서는 멀티미디어, 소셜미디어 등의 다양한 모바일 컴퓨팅이 발생하기 때문에[1], 고성능 컴퓨팅(HPC) 보다는 대규모 컴퓨팅(HTC)이 필요하다[2]. 또한 모바일 컴퓨팅 작업이 모바일 기기의 컴퓨팅 리소스에 어떻게 할당하는지에 대한 상태 파악이 중요하다. 따라서 본 논문에서는 모바일 기기를 통합한 모바일 클라우드내 대규모 컴퓨팅을 위한 모바일 작업 할당 시뮬레이터(JAS-HTC)를 제안한다. JAS-HTC는 모바일 컴퓨팅의 작업 할당을 시각적으로 표현하여, 대규모 컴퓨팅 작업 처리의 상태를 파악할 수 있도록 한다.

• The Transactions of the Korea Information Processing Society
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• v.7 no.6
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• pp.1941-1948
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• 2000

Multistage interconnection networks (MINs) have been recognized as an efficient interconnection network for high-performance computer systems and also have been recently identified to be effective for a switching fabric of new communication structures - gigabit ethernet switch, terabit router, and ATM (asynchronous transfer mode). While lots of models analyzing the performance of MINs have been proposed, they are either inaccurate or, even if accurate, very complex for the analysis. In this paper, we propose an extremely simple mode for evaluating the multibuffered MIN with small clock cycles based on the approximation approach. Comprehensive computer simulation shows that the proposed model is very accurate in terms of the throughput and mean delay. Furthermore, it significantly reduces the computing overhead due to its simplicity.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.11
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• pp.5252-5268
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• 2018

To support a large-scale Hadoop cluster, Hadoop heartbeat messages are designed to deliver the significant messages, including task scheduling and completion messages, via piggybacking to reduce the number of messages received by the NameNode. Although Hadoop is designed and optimized for high-throughput computing via batch processing, the real-time processing of large amounts of data in Hadoop is increasingly important. This paper evaluates Hadoop's performance and costs when the heartbeat period is controlled to support latency sensitive applications. Through an empirical study based on Hadoop 2.0 (YARN) architecture, we improve Hadoop's I/O performance as well as application performance by up to 13 percent compared to the default configuration. We offer a guideline that predicts the performance, costs and limitations of the total system by controlling the heartbeat period using simple equations. We show that Hive performance can be improved by tuning Hadoop's heartbeat periods through extensive experiments.

• Proceedings of the Korean Society for Bioinformatics Conference
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• 2003.10a
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• pp.1-1
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• 2003

It is clear that computers will play a key role in the biology of the future. Even now, it is virtually impossible to keep track of the key proteins, their names and associated gene names, physical constants(e.g. binding constants, reaction constants, etc.), and hewn physical and genetic interactions without computational assistance. In this sense, computers act as an auxiliary brain, allowing one to keep track of thousands of complex molecules and their interactions. With the advent of gene expression array technology, many experiments are simply impossible without this computer assistance. In the future, as we seek to integrate the reductionist description of life provided by genomic sequencing into complex and sophisticated models of living systems, computers will play an increasingly important role in both analyzing data and generating experimentally testable hypotheses. The future of bioinformatics is thus being driven by potent technological and scientific forces. On the technological side, new experimental technologies such as microarrays, protein arrays, high-throughput expression and three-dimensional structure determination prove rapidly increasing amounts of detailed experimental information on a genomic scale. On the computational side, faster computers, ubiquitous computing systems, high-speed networks provide a powerful but rapidly changing environment of potentially immense power. The challenges we face are enormous: How do we create stable data resources when both the science and computational technology change rapidly? How do integrate and synthesize information from many disparate subdisciplines, each with their own vocabulary and viewpoint? How do we 'liberate' the scientific literature so that it can be incorporated into electronic resources? How do we take advantage of advances in computing and networking to build the international infrastructure needed to support a complete understanding of biological systems. The seeds to the solutions of these problems exist, at least partially, today. These solutions emphasize ubiquitous high-speed computation, database interoperation, federation, and integration, and the development of research networks that capture scientific knowledge rather than just the ABCs of genomic sequence. 1 will discuss a number of these solutions, with examples from existing resources, as well as area where solutions do not currently exist with a view to defining what bioinformatics and biology will look like in the future.

• Journal of the Korea Society for Simulation
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• v.20 no.4
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• pp.139-147
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• 2011

There is a growing tendency toward a vehicle demand and a utilization of traffic information systems. Due to various kinds of traffic information systems and increasing of communication data, the traffic information service requires a very high IT infrastructure. A cloud computing environment is an essential approach for reducing a IT infrastructure cost. And the traffic information service needs a provisioning scheduling method for managing a resource. So we propose a provisioning scheduling with conditional probability inference (PSCPI) for the traffic information service on cloud environment. PSCPI uses a naive bayse inference technique based on a status of a virtual machine. And PSCPI allocates a job to the virtual machines on the basis of an availability of each virtual machine. Naive bayse based PSCPI provides a high throughput and an high availability of virtual machines for real-time traffic information services.

• Journal of Information Processing Systems
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• v.16 no.4
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• pp.845-858
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• 2020

This paper proposes a modified end-to-end secure low energy adaptive clustering hierarchy (ME-LEACH) algorithm for enhancing the lifetime of a wireless sensor network (WSN). Energy limitations are a major constraint in WSNs, hence every activity in a WSN must efficiently utilize energy. Several protocols have been introduced to modulate the way a WSN sends and receives information. The end-to-end secure low energy adaptive clustering hierarchy (E-LEACH) protocol is a hierarchical routing protocol algorithm proposed to solve high-energy dissipation problems. Other methods that explore the presence of the most powerful nodes on each cluster as cluster heads (CHs) are the sparsity-aware energy efficient clustering (SEEC) protocol and an energy efficient clustering-based routing protocol that uses an enhanced cluster formation technique accompanied by the fuzzy logic (EERRCUF) method. However, each CH in the E-LEACH method sends data directly to the base station causing high energy consumption. SEEC uses a lot of energy to identify the most powerful sensor nodes, while EERRCUF spends high amounts of energy to determine the super cluster head (SCH). In the proposed method, a CH will search for the nearest CH and use it as the next hop. The formation of CH chains serves as a path to the base station. Experiments were conducted to determine the performance of the ME-LEACH algorithm. The results show that ME-LEACH has a more stable and higher throughput than SEEC and EERRCUF and has a 35.2% better network lifetime than the E-LEACH algorithm.

• Journal of KIISE:Computing Practices and Letters
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• v.11 no.1
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• pp.92-99
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• 2005

In this paper, we present a high-level design methodology applied on a network system-on-a-chip(SOC) using SystemC. The main target of our approach is to get optimum performance parameters for high network address translation(NAT) throughput. The Fast Ethernet media access controller(MAC) and its direct memory access(DMA) controller are modeled with SystemC in transaction level. They are calibrated through the cycle-based measurement of the operation of the real Verilog register transfer language(RTL). The NAT throughput of the model is within $\pm$10% error compared to the output of the real evaluation board. Simulation speed of the model is more than 100 times laster than the RTL. The validated models are used for intensive architecture exploration to find the performance bottleneck in the NAT router.