• The Transactions of the Korea Information Processing Society
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• v.2 no.1
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• pp.66-74
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• 1995

A 8-bit 15MHz CMOS subranging Analog-to-Digital converter for high-speed, low-power consumption applications is described. Subranging, 2 step flash, A/D converter used a new resistor string and a simple comparator architecture for the low power consumption and small chip area. Comparator exhibites 80dB loop gain, 50MHz conversion speed, 0.5mV offset and maximum error of voltage divider was 1mV. This Analog-to-Digital converter has been designed and fabricated in 1.2 m N-well CMOS technology. It consumed 150mW power at ＋5/-5V supply and delayed 65ns. The proposed Analog-to-Digital converter seems suitable for high- speed, low-power consumption, small area applications and one-chip mixed Analog- Digital system. Simulations are performed with PSPICE and a fabricated chip is tested.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.2
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• pp.153-160
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• 1999

Dual-stage servo system for super-high density HDD has the chances of being composed of the coarse actuator(VCM) for track-seeking control and the fine actuator(microactuator) for-following control in near future. This paper presents the concept design of dual-stage servo system and the track-following control using an electrostatic microactuator for super-high density HDD. The electrostatic microactuator is designed and fabricated by MEMS(micro-electro-mechanical system) process. Both the nonlinear plant(voltage/displacement-to-electrostatic force) and the linear plant(electrostatic force-to-displacement) of the microactuator are established. Inverse function of the nonlinear plant is employed for a feedforward nonlinear compensator design. And feedforward control effect of this compensator is shown by time-domain experiments. A track-following feedback controller is designed using the feedback nonlinear compensator which is derived from the feedforward nonlinear compensator. The track-following control experiment is done to show the control efficiency of the proposed control system. And, excellent track-following control performance(2.21kHz servo-bandwidth, 7.51dB gain margin, $50.98^{\circ}$phase margin) is achieved by the proposed control system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38B no.6
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• pp.427-434
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• 2013

In this paper, the design and layout of a 2.5 Gbps arrayed VCSEL driver for optical transceiver having arrayed multi-channel of integrating module is confirmed. In this paper, a 4 channel 2.5 Gbps VCSEL (vertical cavity surface emitting laser) driver array with automatic optical power control is implemented using $0.18{\mu}m$ CMOS process technology that drives a $1550{\mu}m$ high speed VCSEL used in optical transceiver. To enhance the bandwidth of the optical transmitter, active feedback amplifier with negative capacitance compensation is exploited. We report a distinct improvement in bandwidth, voltage gain and operation stability at 2.5Gbps data rate in comparison with existing topology. The 4-CH chip consumes only 140 mW of DC power at a single 1.8V supply under the maximum modulation and bias currents, and occupies the die area of $850{\mu}m{\times}1,690{\mu}m$ excluding bonding pads.

• Journal of IKEEE
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• v.19 no.4
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• pp.506-513
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• 2015

In this paper, an output-capacitorless, low-dropout (LDO) regulator is designed, which consumes $4.5{\mu}A$ quiescent current. Proposed LDO regulator is realized using two amplifier for good load regulation and fast response time, which provide high gain, high bandwidth, and high slew rate. In addition, a one-shot current boosting circuit is added for current control to charge and discharge the parasitic capacitance at the pass transistor gate. As a result, response time is improved during load-current transition. The designed circuit is implemented through a $0.11-{\mu}m$ CMOS process. We experimentally verify output voltage fluctuation of 260mV and recovery time of $0.8{\mu}s$ at maximum load current 200mA.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.12
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• pp.40-48
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• 2013

This paper presents multi-channel transimpedance amplifier(TIA) arrays in short-range LADAR systems for unmanned vehicles, by using a 0.18um CMOS technology. Two $4{\times}4$ channel TIA arrays including a voltage-mode INV-TIA and a current-mode CG-TIA are introduced. First, the INV-TIA consists of a inverter stage with a feedback resistor and a CML output buffer with virtual ground so as to achieve low noise, low power, easy current control for gain and impedance. Second, the CG-TIA utilizes a bias from on-chip bandgap reference and exploits a source-follower for high-frequency peaking, yielding 1.26 times smaller chip area per channel than INV-TIA. Post-layout simulations demonstrate that the INV-TIA achieves 57.5-dB${\Omega}$ transimpedance gain, 340-MHz bandwidth, 3.7-pA/sqrt(Hz) average noise current spectral density, and 2.84mW power dissipation, whereas the CG-TIA obtains 54.5-dB${\Omega}$ transimpedance gain, 360-MHz bandwidth, 9.17-pA/sqrt(Hz) average noise current spectral density, and 4.24mW power dissipation. Yet, the pulse simulations reveal that the CG-TIA array shows better output pulses in the range of 200-500-Mb/s operations.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.10
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• pp.109-117
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• 2004

In this paper, a K-band local oscillator composed of a VCDRO(Voltage Controlled Dielectric Resonator Oscillator), GaAs MESFET, and Reflector type frequency doubler has been designed and fabricated. TO obtain a good phase noise performance of a VCDRO, a active device was selected with a low noise figure and a low flicker noise MESFET and a dielectric resonator was used for selecting stable and high oscillation frequency. Especially, to have a higher conversion gain than a conventional doubler as well as a good harmonic suppression performance with circuit size reduced a doubler structure was employed as the Reflector type composed of a reflector and a open stub of quarter wave length for rejecting the unwanted harmonics. The measured results of fabricated oscillator show that the output power was 5.8 dBm at center frequency 12.05 GHz and harmonic suppression -37.98 dBc, Phase noise -114 dBc at 100 KHz offset frequency, respectively, and measured results show of fabricated frequency doubler, the output power at 5.8 dBm of input power is 1.755 dBm conversion gain 1.482 dB, harmonic suppression -33.09 dBc, phase noise -98.23 dBc at 100 KHz offset frequency, respectively. This oscillator could be available to a local oscillator in K-band which used frequency doubler techniques.

• KIEE International Transactions on Electrophysics and Applications
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• v.5C no.3
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• pp.102-110
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• 2005

Piezoelectric transformers(PT) are expected to be small, thin and highly efficient, and which are attractive as a transformer with high power density for step down voltage. For these reasons, we have attempted to develop a step-down PT for the miniaturized adaptor. We propose a PT, operating in thickness extensional vibration mode for step-down voltage. This PT consists of a multi-layered construction in the thickness direction. In order to develop the step-down PT of 10 W class and turn ratio of 0.1 with high efficiency and miniaturization, the piezoelectric ceramics and PT designs are estimated with a variety of characteristics. The basic composition of piezoelectric ceramics consists of ternary yPb(Zr$_{x}$Ti$_{1-x}$)O$_{3}$-(1-y)Pb(Mn$_{1/3}$Nb1$_{1/3}$Sb$_{1/3}$)O$_{3}$. In the piezoelectric characteristics evaluations, at y=0.95 and x=0.505, the electromechanical coupling factor(K$_{p}$) is 58$\%$, piezoelectric strain constant(d$_{33}$) is 270 pC/N, mechanical quality factor(Qr$_{m}$) is 1520, permittivity($\varepsilon$/ 0) is 1500, and Curie temperature is 350 $^{\circ}C$. At y = 0.90 and x = 0.500, kp is 56$\%$, d33 is 250 pC/N, Q$_{m}$ is 1820, $\varepsilon$$_{33}$$^{T}$/$\varepsilon$$_{0}$ is 1120, and Curie temperature is 290 $^{\circ}C$. It shows the excellent properties at morphotropic phase boundary regions. PZT-PMNS ceramic may be available for high power piezoelectric devices such as PTs. The design of step-down PTs for adaptor proposes a multi-layer structure to overcome some structural defects of conventional PTs. In order to design PTs and analyze their performances, the finite element analysis and equivalent circuit analysis method are applied. The maximum peak of gain G as a first mode for thickness extensional vibration occurs near 0.85 MHz at load resistance of 10 .The peak of second mode at 1.7 MHz is 0.12 and the efficiency is 92$\%$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.329-329
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• 2007

Photoconductive poly crystalline lead oxide coated on amorphous thin film transistor (TFT) arrays is the best candidate for direct digital x-ray detector for medical imaging. Thicker films with lessening density often show lower x-ray induced charge generation and collection becomes less efficient. In this work, we present a new methodology used for the high density deposition of PbO. We investigate the structural properties of the films using X-ray diffraction and electron microscopy experiments. The film coatings of approximately $200\;{\mu}m$ thickness were deposited on $2"{\times}2"$ conductive-coated glass substrates for measurements of dark current and x-ray sensitivity. The lead oxide (PbO) films of $200\;{\mu}m$ thickness were deposited on glass substrates using a wet coating process in room temperature. The influence of post-deposition annealing on the characteristics of the lead oxide films was investigated in detail. X-ray diffraction and scanning electron microscopy, and atomic force microscopy have been employed to obtain information on the morphology and crystallization of the films. Also we measured dark current, x-ray sensitivity and linearity for investigation of the electrical characteristics of films. It was found that the annealing conditions strongly affect the electrical properties of the films. The x-ray induced output charges of films annealed in oxygen gas increases dramatically with increasing annealing temperatures up to $500^{\circ}C$ but then drops for higher temperature anneals. Consequently, the more we increase the annealing temperatures, the better density and film quality of the lead oxide. Analysis of this data suggests that incorporation and decomposition reactions of oxygen can be controlled to change the detection properties of the lead oxide film significantly. Post-deposition thermal annealing is also used for densely film. The PbO films that are grown by new methodology exhibit good morphology of high density structure and provide less than $10\;pA/mm^2$ dark currents as they show saturation in gain (at approximate fields of $4\;V/{\mu}m$). The ability to operate at low voltage gives adequate dark currents for most applications and allows voltage electronics designs.

• Transactions on Electrical and Electronic Materials
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• v.17 no.6
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• pp.341-350
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• 2016

The current study is dedicated to design a novel coordinated controller to effectively increase power system rotor angle stability. In doing so, the coordinated design of an AVR (automatic voltage regulator), PSS2B, and TCSC (thyristor controlled series capacitor)-based POD (power oscillation damping) controller is proposed. Although the recently employed coordination between a CPSS (conventional power system stabilizer) and a TCSC-based POD controller has been shown to improve power system damping characteristics, neglecting the negative impact of existing high-gain AVR on the damping torque by considering its parameters as given values, may reduce the effectiveness of a CPSS-POD controller. Thus, using a technologically viable stabilizer such as PSS2B rather than the CPSS in a coordinated scheme with an AVR and POD controller can constitute a well-established design with a structure that as a high potential to significantly improve the rotor angle stability. The design procedure is formulated as an optimization problem in which the ITSE (integral of time multiplied squared error) performance index as an objective function is minimized by employing an IPSO (improved particle swarm optimization) algorithm to tune adjustable parameters. The robustness of the coordinated designs is guaranteed by concurrently considering some operating conditions in the optimization process. To evaluate the performance of the proposed controllers, eigenvalue analysis and time domain simulations were performed for different operating points and perturbations simulated on 2A4M (two-area four-machine) power systems in MATLAB/Simulink. The results reveal that surpassing improvement in damping of oscillations is achieved in comparison with the CPSS-TCSC coordination.

• The Journal of the Korea institute of electronic communication sciences
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• v.15 no.5
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• pp.827-834
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• 2020

In this paper, a third-order harmonic mixer is designed using frequency multiplier theory for the microwave airborne radar. Unlike the basic mixer design method, the gate bias voltage, at which the third-harmonic component of the Local frequency (LO) is the maximum, is selected using a frequency multiplier theory to maximize the third-harmonic mixing component at the intermediate frequency (IF). The proposed harmonic mixer was designed and manufactured using a commercial GaAs MESFET device in a plastic package, and it was possible to improve the high conversion loss, circuit complexity, high cost, and manufacturing complexity of the existing microwave mixer. The harmonic mixer using the proposed design method has a -8 ~ -10 dB conversion loss by pumping 11.5 GHz LO with a +5 dBm level when operating from 33.0 GHz to 36.0 GHz and the 1-dB gain compression point (P1dB) of 0 dBm.