• 제목/요약/키워드: High level synthesis

검색결과 398건 처리시간 0.021초

시간 제약 조건하에서의 모듈 선택을 고려한 전력감소 스케쥴링 (Reducing Power Consumption of a Scheduling for Module Selection under the Time Constraint)

  • 최지영;박남서;김희석
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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    • pp.1153-1156
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    • 2003
  • In this paper, we present a reducing power consumption of a scheduling for module selection under the time constraint. Traditional high-level synthesis do not allow reuse of complex, realistic datapath component during the task of scheduling. On the other hand, the proposed scheduling of reducing power consumption is able to approach a productivity of the design the low power to reuse which given a library of user-defined datapath component and to share of resource sharing on the switching activity in a shared resource. Also, we are obtainable the optimal the scheduling result in experimental results of our approach various HLS benchmark environment using chaining and multi-cycling in the scheduling techniques..

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조건부 자원 공유를 고려한 스케쥴링 알고리즘 (A scheduling algorithm for conditonal resources sharing consideration)

  • 인지호;정정화
    • 전자공학회논문지A
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    • 제33A권2호
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    • pp.196-204
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    • 1996
  • This paper presents a new scheduling algorithm, which is the most improtant subtask in the high level synthesis. The proposed algorithm performs scheduling in consideration of resource sharing concept based on characteristics of conditionsla bransches in the intermediate data structure. CDFG (control data flow graph) generated by a VHDL analyzer. This algorithm constructs a conditon graph based on time frame of each operation using both the ASAP and the ALAP scheduling algorithm. The conditon priority is obtained from the condition graph constructed from each conditional brance. The determined condition priority implies the sequential order of transforming the CDFG with conditonal branches into the CDFG without conditional branches. To minimize resource cost, the CDFG with conditional branches are transformed into the CDFG without conditonal brancehs according to the condition priority. Considering the data dependency, the hardware constraints, and the data execution time constraints, each operation in the transformed CDFG is assigned ot control steps. Such assigning of unscheduled operations into contorl steps implies the performance of the scheduling in the consecutive movement of operations. The effectiveness of this algorithm is hsown by the experiment for the benchmark circuits.

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제한조건을 고려한 효율적 회로 설계 알고리즘 (An efficient circuit design algorithm considering constraint)

  • 김재진
    • 디지털산업정보학회논문지
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    • 제8권1호
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    • pp.41-46
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    • 2012
  • In this paper, An efficient circuit design algorithm considering constraint is proposed. The proposed algorithm sets up in time constraint and area constraint, power consumption constraint for a circuit implementation. First, scheduling process for time constraint. Select the FU(Function Unit) which is satisfied with time constraint among the high level synthesis results. Analyze area and power consumption of selected FUs. Constraint set for area and power constraint. Device selection to see to setting condition. Optimization circuit implementation in selected device. The proposed algorithm compared with [7] and [8] algorithm. Therefore the proposed algorithm is proved an efficient algorithm for optimization circuit implementation.

An Efficient Topology/Parameter Control in Evolutionary Design for Multi-domain Engineering Systems

  • Seo, Ki-Sung
    • International Journal of Fuzzy Logic and Intelligent Systems
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    • 제5권2호
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    • pp.108-113
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    • 2005
  • This paper suggests a control method for an efficient topology/parameter evolution in a bond graph-based GP design framework that automatically synthesizes designs for multi-domain, lumped parameter dynamic systems. We adopt a hierarchical breeding control mechanism with fitness-level-dependent differences to obtain better balancing of topology/parameter search - biased toward topological changes at low fitness levels, and toward parameter changes at high fitness levels. As a testbed for this approach in bond graph synthesis, an eigenvalue assignment problem, which is to find bond graph models exhibiting minimal distance errors from target sets of eigenvalues, was tested and showed improved performance for various sets of eigenvalues.

A Resource-constrained Scheduling Algorithm for High-level Synthesis

  • Song, Ho-Jeong;Lee, Jae-Jin;Hwang, In-Jae;Song, Gi-Yong
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2002년도 ITC-CSCC -3
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    • pp.1728-1731
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    • 2002
  • Scheduling is assigning each operation in a control/data flow graph(CDFG) to a specific control step. It directly influences the performance of the hardware synthesized. In this paper, we propose an efficient resource-constrained scheduling algorithm assuming that only available silicon area is given. We performed the experiment to evaluate its performance. The results show that our algorithm find the solution with shorter scheduling length compared to the existing methods.

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상위단계 합성에서의 전압 할당을 결합한 자원공유 (Resource Sharing Combined with Voltage Assignment in High-level Synthesis)

  • 김동현;김태환
    • 한국정보과학회:학술대회논문집
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    • 한국정보과학회 2005년도 한국컴퓨터종합학술대회 논문집 Vol.32 No.1 (A)
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    • pp.721-723
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    • 2005
  • 상위 단계 합성에서의 자원 공유 (또는 바인딩)는 최종회로 결과의 질에 심각한 영향을 미치는 중요한 작업들 가운데 하나이다. 기존의 자원 공유 기법의 목적은 주어진 자원 제약 조건하에서 회로의 지연 시간을 최소화하거나, 주어진 지연시간 조건하에서 하드웨어의 복잡도 (예: 회로 면적)를 최소화하는 것이다. 본 논문에서는, 자원 공유 문제를 회로에서 소모되는 전력 소모를 줄이는 각도에서 보고 있다. 구체적으로, 전압 배정 작업을 자원 공유 문제와 결합하여, 두 개의 작업을 통합된 방식으로 해결함으로서 회로 결과에서의 소모되는 전력 소모량을 충분히 그리고 효과적으로 줄이는데 목표를 두고 있다. 벤치마크를 사용한 실험에서 우리는 제안한 방법을 사용하면, 기존의 순차적인 자원 공유와 전압 배정 적용 방식보다 $0.7\%-16\%$ 더 적은 전력 소모를 가짐을 알 수 있었다.

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PVDF/ZnO Nanopillar 복합재료를 이용한 압전필름 스피커의 성능향상 (Enhanced Performance of PVDF Piezoelectric Speaker Using PVDF/ZnO Nanopillar Composites)

  • 곽준혁;허신
    • 센서학회지
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    • 제25권6호
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    • pp.447-452
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    • 2016
  • In this study, we fabricated and evaluated the performance of film speaker using PVDF/ZnO NP composite structure. PVDF piezoelectric films were fabricated and characterized by XRD and SEM. ZnO nanopillars were prepared by hydrothermal synthesis on prepared PVDF piezoelectric films. We analyzed and tested the acoustic signal characteristics of the piezoelectric film. In order to fabricate an acoustic structure with a wide frequency range from low to high frequency, we have fabricated various types of film speakers and investigated the frequency characteristics. As a result, the fundamental piezoelectric properties of PVDF show that the piezoelectric constant due to ZnO NP increases. And the overall acoustic signal level is also increased by 10% or more. We investigated frequency generation from 500 Hz to 10 KHz using different sizes with PVDF/ZnO NP composite film speaker.

시간제약 조건하에서 재사용 모듈 설계를 통한 CPLD 저전력 기술 매핑 (CPLD Low Power Technology Mapping for Reuse Module Design under the Time Constraint)

  • 강경식
    • 디지털산업정보학회논문지
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    • 제4권3호
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    • pp.77-83
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    • 2008
  • In this paper, CPLD low power technology mapping for reuse module design under the time constraint is proposed. Traditional high-level synthesis do not allow reuse of complex, realistic datapath component during the task of scheduling. On the other hand, the proposed algorithm is able to approach a productivity of the design the low power to reuse which given a library of user-defined datapath component and to share of resource sharing on the switching activity in a shared resource. Also, we are obtainable the optimal the scheduling result in experimental results of our using chaining and multi-cycling in the scheduling techniques. Low power circuit make using CPLD technology mapping algorithm for selection reuse module by scheduling.

젖소 유방염유래(乳房炎由來) Gram 음성간균(陰性桿菌)의 Ampicillin 내성(耐性) 및 전달성(傳達性) β-Lactamase Plasmids (Ampicillin Resistance and Transferable β-Lactamase Plasmids of Gram Negative Rods Isolated from Bovine Mastitis)

  • 박청규
    • 대한수의학회지
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    • 제25권1호
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    • pp.61-67
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    • 1985
  • One hundred and twenty seven strains of Gram-negative rods (72 E. coli, 45 Klebsieila pneumoniae, 8 Enterobacter spp. and 2 Pseudomonas aeruginosa) isolated from bovine mastitis were examined for resistance to ampicilin, carbenicillin and cefazolin, ${\beta}$-lactamase activity and transferable ${\beta}$-lactamase plasmids. Stains resistant to ampicillin were 13.9% in E. coli, 93.3% in Klebsiella pneumoniae, 87.5% in Enterobacter. spp. and all in Pseudomonas aeruginosa, Resistance of E. coli, Klebsiella pneumoniae and Enterobacter spp. to ampicillin was due to the ${\beta}$-lactamases, but all Pseudomonas aeruginosa exhibited a high level of the non-enzymic resistance. Transferable plasmid-mediated ${\beta}$-lactamase synthesis was demonstrated in 61.9% of Klebsiella pneumoniae, 50% of E. coli and 42.9% of Enterobacter spp. The same ${\beta}$-lactamase plasmids specified different resistance levels to various ${\beta}$-lactam antibiotics in different recipients.

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Synthesis and evaluation of inhibitors for Polo-box domain of Polo-like kinase 1

  • Eun Kyoung Ryu
    • 대한방사성의약품학회지
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    • 제6권2호
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    • pp.139-145
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    • 2020
  • Polo-like kinase 1 (Plk1) is a key protein in mitosis and has been validated as a target for tumor therapy. It is well known to highly overexpress in many kinds of tumor, which has been implicated as a potential biomarker for tumor treatment and diagnosis. Plk1 consists of two domains, the N-terminus kinase domain and the C-terminus polo-box domain (PBD). The inhibitors have been developed for PBD of Plk1, which were shown a high level of affinity and selectivity for Plk1 that led to mitotic arrest and apoptotic cell death. This review discusses the inhibitors for PBD of Plk1 that are suitable for in vivo tumor treatment. They can be further extended for developing in vivo imaging probes for early diagnosis of tumor.