• Title/Summary/Keyword: High Speed Timer

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A Fault Tolerance Mechanism with Dynamic Detection Period in Multiple Gigabit Server NICs (다중 Gigabit Server NICs에서 동적 검출 주기를 적용한 결함 허용 메커니즘)

  • 이진영;이시진
    • Journal of Internet Computing and Services
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    • v.3 no.5
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    • pp.31-39
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    • 2002
  • A rapid growth of internet and sudden increase of multimedia data demands for high-speed transfer media and if optimizec usage from the interface system. To achieve this level of network bandwidth, multiple NICs for support of high-speed network bandwidth have been developed and studied. Furthermore, the use of multiple NICs can provide high-speed LAN environment without large network environment modification, supports backward compatibility of current system and reduce overhead. However. if system failure is caused by SPOF(Single Point of Failure) fault of large-capacity multiple NICs, incredible loss will be met because it services large capacity of multimedia data, Therefore, to prevent loss coming from faults, we describe 'Fault tolerance of multiple NICs', which use the fault prevention mechanism. Considering inefficiency of availability and serviceability that is occurred with existing TMR, Primary-Standby approach and Watchdog time mechanism, we propose and design the efficient fault tolerance mechanism, which minimize down time as changing of detection period dynamically. Consequently, the fault tolerance mechanism proposed for reducing overhead time when the fault is occurred, should minimize system downtime overall.

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Enhancing TCP Performance to Persistent Packet Reordering

  • Leung Ka-Cheong;Ma Changming
    • Journal of Communications and Networks
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    • v.7 no.3
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    • pp.385-393
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    • 2005
  • In this paper, we propose a simple algorithm to adaptively adjust the value of dupthresh, the duplicate acknowledgement threshold that triggers the transmission control protocol (TCP) fast retransmission algorithm, to improve the TCP performance in a network environment with persistent packet reordering. Our algorithm uses an exponentially weighted moving average (EWMA) and the mean deviation of the lengths of the reordering events reported by a TCP receiver with the duplicate selective acknowledgement (DSACK) extension to estimate the value of dupthresh. We also apply an adaptive upper bound on dupthresh to avoid the retransmission timeout events. In addition, our algorithm includes a mechanism to exponentially reduce dupthresh when the retransmission timer expires. With these mechanisms, our algorithm is capable of converging to and staying at a near-optimal interval of dupthresh. The simulation results show that our algorithm improves the protocol performance significantly with minimal overheads, achieving a greater throughput and fewer false fast retransmissions.

Dynamic timer Mechanism for Advanced TCP-DAD at High-speed Network (고속 네트워크에서 동적인 타이머 조절 기법을 통한 향상된 TCP-DAD)

  • Kang, Dong-Min;Park, Min-Woo;Park, Sun-Ho;Chung, Tai-Myoung
    • Proceedings of the Korea Information Processing Society Conference
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    • 2009.04a
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    • pp.1348-1351
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    • 2009
  • 패킷 재배치(packet reodering)는 전송한 패킷의 순서가 처음과 다르게 뒤섞여 수신지에 도착하는 현상을 의미한다. 패킷 재배치는 불필요한 재전송이나 불필요한 혼잡 제어를 수행하여 TCP의 성능을 저하시킨다. 패킷 재배치에 의한 TCP 성능 저하를 막기 위해 다양한 접근 방법이 소개되었다. TCP-DAD는 기존 TCP에서 3으로 고정된 중복 응답 임계값을 동적으로 조절하여, 잘못된 혼잡 제어를 예방하고 있다. 일반적으로 전송한 패킷의 수가 많을 때, 패킷 재배치를 경험할 확률이 높으며, 패킷 재배치에 의해 잘못된 혼잡 제어가 일어날 가능성 많다. 고속 네트워크 환경에서는 혼잡 윈도우 크기 변화의 폭이 매우 크다는 점을 고려할 때, 중복 응답 임계값을 조절하는 TCP-DAD는 한계가 있다. 본 논문에서는 고속 네트워크 환경에서의 패킷 재배치 현상으로 인한 TCP 성능저하를 완화하기 위한 새로운 알고리즘 TCP-DT를 소개한다. 이는 중복 응답 수에 의존하지 않고 타이머를 통해 혼잡 제어를 수행하는 메커니즘 이다. 본 논문은 NS-2를 사용하여 고속 네트워크 환경에서의 시뮬레이션을 통해 제안한 TCP-DT의 성능 향상을 증명하였다.

Development of Vehicle LDW Application Service using AUTOSAR Platform on Multi-Core MCU (멀티코어 상의 AUTOSAR 플랫폼을 활용한 차량용 LDW 응용 서비스 개발)

  • Park, Mi-Ryong;Kim, Dongwon
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.14 no.4
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    • pp.113-120
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    • 2014
  • In this paper, we examine Asymmetric Multi-Processing Environment to provide LDW service. Asymmetric Multi-Processing Environment consists of high-speed MCU to support rapid image processing and low-speed MCU for controlling with other ECU at the control domain. Also we designed rapid image process application and LDW application Software Component(SW-C) according to the development process rule of AUTOSAR. To communicate between two MCUs, timer based polling based IPC was designed. Also to communicate with other ECUs(Electronic Control Units), we designed CAN messages to provide alarm information and receiving CAN message to catch the Turn signal. We confirm the possibility of the various ADAS development using an Asymmetric Multi-Processing Environment and AUTOSAR platform. We also expect providing ISO 26262 functional safety.

Development of Automatic Remote Exposure Controller for Gamma Radiography (감마선투과검사 장치의 자동 원격조작기 개발)

  • Joo, Gwang-Tae;Shin, Jin-Seong;Kim, Dong-Eun;Song, Jung-Ho;Choo, Seung-Hwan;Chang, Hong-Keun
    • Journal of the Korean Society for Nondestructive Testing
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    • v.22 no.5
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    • pp.490-499
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    • 2002
  • Recently, gamma radiographic equipments have been used about 1,000 sets manually and operated by about 2,500 persons in Korea. In order for a radiography to work effectively with avoiding any hazard of the high level radiation from the source, many field workers have expected developing a wireless automatic remote exposure controller. The KlTCO research team has developed an automatic remote exposure controller that can regulate the speed of $0.4{\sim}1.2m/s$ by BLDC motor of 24V 200W which has output of $54kgf{\cdot}cm$, suitable torque and safety factor for the work. And the developed automatic remote exposure controller can control rpm of motor, pigtail position by photo-sensor and exposure time by timer to RF sensor. Thus, the developed equipment is expected that the unit can be used in many practical applications with benefits in economical advantage to combine the use of both automatic and manual type because attachment is possible existent manual remote exposure controller, AC and DC combined use.

Implementation of the Digital Current Control System for an Induction Motor Using FPGA (FPGA를 이용한 유도 전동기의 디지털 전류 제어 시스템 구현)

  • Yang, Oh
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.35C no.11
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    • pp.21-30
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    • 1998
  • In this paper, a digital current control system using a FPGA(Field Programmable Gate Array) was implemented, and the system was applied to an induction motor widely used as an industrial driving machine. The FPGA designed by VHDL(VHSIC Hardware Description Language) consists of a PWM(Pulse Width Modulation) generation block, a PWM protection block, a speed measuring block, a watch dog timer block, an interrupt control block, a decoder logic block, a wait control block and digital input and output blocks respectively. Dedicated clock inputs on the FPGA were used for high-speed execution, and an up-down counter and a latch block were designed in parallel, in order that the triangle wave could be operated at 40 MHz clock. When triangle wave is compared with many registers respectively, gate delay occurs from excessive fan-outs. To reduce the delay, two triangle wave registers were implemented in parallel. Amplitude and frequency of the triangle wave, and dead time of PWM could be changed by software. This FPGA was synthesized by pASIC 2SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to digital current control system for 3-phase induction motor. The digital current control system of the 3 phase induction motor was configured using the DSP(TMS320C31-40 MHz), FPGA, A/D converter and Hall CT etc., and experimental results showed the effectiveness of the digital current control system.

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Performance Analysis of The CCITT X.25 Protocol (X. 25 Protocol의 성능 분석)

  • 최준균;은종관
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.11 no.1
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    • pp.25-39
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    • 1986
  • In this paper, we analyze the performance, particularly the flow control mechanism, of the CCITT X.25 protocol in a packet-switched network. In this analysis, we consider the link and packet layers separately, and investigate the performance in three measures; normalized channel throughput, mean transmission time, and transmission efficiency. Each of these measures is formulated in terms of given protocol parameters such as windos size, $T_1$ and $T_2$ values, message length, and so forth. We model the service procedure of the inpur traffic based on the flow control mechanism of the X.25 protocol, and investigate the mechanism of the sliding window flow control with the piggybacked acknowlodgment scheme using a discrete-time Markov chain model. With this model, we study the effect of variation of the protoccol parameters on the performance of the X.25 protocol. From the numerical results of this analysis one can select the optimal valuse of the protocol parameters for different channel environments. it has been found that to maintain the trasnmission capacity satisfactorily, the window size must be greater than or equal to 7 in a high-speed channel. The time-out value, $T_1$, must carefully be selected in a noisy channel. In a normal condition, it should be in the order of ls. The value of $T_2$ has some effect on the transmission efficiency, but is not critical.

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