• Title/Summary/Keyword: Heating channel layout

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A Study of Evaluation Technology for Heating Channel Layout in SMC Molds (SMC 금형의 가열채널레이아웃 평가기술에 관한 연구)

  • 이성희;고영배;이종훈
    • Proceedings of the Korean Society of Precision Engineering Conference
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    • 2004.10a
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    • pp.580-584
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    • 2004
  • In the present study, an evaluation technology for heating channel layout was investigated in SMC molding system design. Conventional design rules of cooling channel in injection molding process were applied to the present work. Finite element thermal analysis with ANSYSTM was performed to evaluate the temperature distribution of mold surface. SMC mold was manufactured to test the effect of a proposed heating channel layout system on the temperature distribution of mold surface and infrared camera was applied to a measurement of temperature. It was shown that infrared camera application was possible in a measurement of temperature distribution on mold surface.

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Beating Channel Layout Design and Evaluation Technology for SMC Molds (Sheet Molding Compound 금형의 가열채널설계 및 평가기술)

  • Heo Y. M.;Ko Y. B.;Lee J. H.;Lee S. H.
    • Transactions of Materials Processing
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    • v.14 no.3 s.75
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    • pp.263-268
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    • 2005
  • Heating channel layout design and evaluation technology for SMC molding system was investigated in this work. Traditional rules of cooling channel design in injection molding were applied to the present work. Finite element thermal analysis with $ANSYS^{TM}$ was performed to evaluate the temperature distribution of SHC mold surface. SMC mold was manufactured to evaluate the effect of a proposed heating channel layout system on the temperature distribution of SMC mold surface and infrared camera was applied to a measurement of temperature distribution. It was shown that infrared camera application was possible in a measurement of temperature distribution on SHC mold surface.

Thermal Resistance Characteristics and Fin-Layout Structure Optimization by Gate Contact Area of FinFET and GAAFET (FinFET 및 GAAFET의 게이트 접촉면적에 의한 열저항 특성과 Fin-Layout 구조 최적화)

  • Cho, Jaewoong;Kim, Taeyong;Choi, Jiwon;Cui, Ziyang;Xin, Dongxu;Yi, Junsin
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.34 no.5
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    • pp.296-300
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    • 2021
  • The performance of devices has been improved with fine processes from planar to three-dimensional transistors (e.g., FinFET, NWFET, and MBCFET). There are some problems such as a short channel effect or a self-heating effect occur due to the reduction of the gate-channel length by miniaturization. To solve these problems, we compare and analyze the electrical and thermal characteristics of FinFET and GAAFET devices that are currently used and expected to be further developed in the future. In addition, the optimal structure according to the Fin shape was investigated. GAAFET is a suitable device for use in a smaller scale process than the currently used, because it shows superior electrical and thermal resistance characteristics compared to FinFET. Since there are pros and cons in process difficulty and device characteristics depending on the channel formation structure of GAAFET, we expect a mass-production of fine processes over 5 nm through structural optimization is feasible.