• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.11B
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• pp.1612-1619
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• 2001

This paper examines the design, implementation characteristics of a folded dipole active integrated antenna. Our goal was to minimize the physical size of RF circuit and its insertion loss, and to make the high frequency tuning easier by directly integrating the ISM(Industrial Scientific & Medical) band power amplifier and antenna. Non-linear model has been used for highly accurate simulation of the power amplifier. The maximum power level was found by using the Load pull method before an impedance matching was achieved. It is found that the total power-added efficiency(PAE) including the driving amplifier was 31.5% and that the transmit power was 13.7 dBm. We also found that the proposed scheme with the smaller antenna as compared with the existing dipole antenna has 23.7 dB total gain including the antenna gain. The suppression of the second harmonic signal to the fundamental signal with respect to the fundamental signal was found to be more than 30 dBc.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.12
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• pp.78-83
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• 2010

In this paper, a novel dual-band power amplifier using metamaterials has been realized with one RF GaN HEMT diffusion metal-oxide-semiconductor field effect transistor. The CRLH TL can lead to metamaterial transmission line with the dual-band tuning capability. The dual-band operation of the CRLH TL is achieved by the frequency offset and the nonlinear phase slope of the CRLH TL for the matching network of the power amplifier. We have managed only the second- and third-harmonics to obtain the high efficiency with the CRLH TL in dual-band. Also, the proposed power amplifier has been realized by using the harmonic control circuit for not only the output matching network, but also the input matching network for better efficiency. Two operating frequencies are chosen at 900 MHz and 2140 MHz in this work. The measured results show that the output power of 39.83 dBm and 35.17 dBm was obtained at 900 MHz and 2140 MHz, respectively. At this point, we have obtained the power-added efficiency (PAE) and IMD of 60.2 %, -23.17dBc and 67.3 %, -25.67dBc at two operation frequencies, respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.7
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• pp.1182-1190
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• 2001

In this paper, microstrip photonic bandgap (PBG) structure with special perforation patterns etched on the line itself is analyzed and optimized in shape, then used for harmonic tuning of power amplifier. This PBG has an advantage in being fabricated and grounded. The dimension of unit lattice is enlarged vertically, but its input and output line maintain 50 Ω using tapered line. This modification from original structure can lessen possible error in etching PCB. The analysis and design of PBG structure are acquired from using EM simulation. The measured insertion loss of the final structure is 0.3 ∼0.4 dB, and its bandwidth of stopband is 6∼7 GHz. Measured results of improved characteristics by using PBG structure at the output of the power amplifier are 0.72∼0.99 dB in output power, 1.14∼7.8 % in PAE, and 1 dBc in the third IMD.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.6
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• pp.670-680
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• 2010

A low power single-chip CMOS receiver for 60 GHz mobile application are proposed in this paper. The single-chip receiver consists of a 4-stage current re-use LNA with under 4 dB NF, Cgs compensating resistive mixer with -9.4 dB conversion gain, Ka-band low phase noise VCO with -113 dBc/Hz phase noise at 1 MHz offset from 26.89 GHz, high-suppression frequency doubler with -0.45 dB conversion gain, and 2-stage current re-use drive amplifier. The size of the fabricated receiver using a standard 0.13 ${\mu}m$ CMOS technology is 2.67 mm$\times$0.75 mm including probing pads. An RF bandwidth is 6.2 GHz, from 55 to 61.2 GHz and an LO tuning range is 7.14 GHz, from 48.45 GHz to 55.59 GHz. The If bandwidth is 5.25 GHz(4.75~10 GHz) The conversion gain and input P1 dB are -9.5 dB and -12.5 dBm, respectively, at RF frequency of 59 GHz. The proposed single-chip receiver describes very good noise performances and linearity with very low DC power consumption of only 21.9 mW.