• Title/Summary/Keyword: Hardware simulator

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Development of Simulator for AIS Algorithm Verification (AIS 알고리즘 검증용 시뮬레이터 개발)

  • Lee, Hyo-Sung;Lee, Seung-Min;Lee, Heung-Ho
    • Proceedings of the KIEE Conference
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    • 2005.10b
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    • pp.478-480
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    • 2005
  • The AIS(Automatic Identification System) transmits the position of ships and other information to prevent accidents which could occur in the sea. It has to be developed SOTDMA(Self-Organized Time Division Multiple Access) Algorithm which is important on wireless communication method for the AIS because It is based on ITU(International Telecommunication Union) M.1371-1 of the international standard therefore, we need to develop a performance evaluation simulator efficiently to develop and analyze SOTDMA Algorithm. This paper shows the method of designing it. Real ships access The VHF maritime mobile band but in this performance evaluation simulator several ship objects access the shared memory. Real ships are designed as the object and the wireless communication channel is designed as the shared memory. The ships apply for real virtual data which got from assistance hardware and The SOTDMA Algorithm driving state verifies the performance evaluation simulator by IEC(International Electrotechnical commission) 61993-2. After verifying results the performance evaluation simulator is correctly satisfied with IEC 61993-2. So we expect that it helps not only the AIS technology developed but also verify new SOTDMA Algorithm.

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Design and Implementation of a Testbed for the Development of KSLV-II Onboard Equipment Simulator (한국형발사체 탑재장비 시뮬레이터 개발을 위한 테스트베드 설계 및 구축)

  • Yoon, Won-Ju
    • Aerospace Engineering and Technology
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    • v.12 no.2
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    • pp.173-179
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    • 2013
  • This paper describes a testbed that was designed and implemented for the development of KSLV-II onboard equipment simulator. It used the CPCI-based industrial hardware system for scalability and the QNX real-time operating system for reliability and real-time simulation. In addition, a real-time application under QNX for function simulations of the KSLV-I PDU was developed and it was verified through interface experiments with KSLV-I upper-stage test equipment. The implemented simulator testbed will be used to verify the development feasibility in the design and development phase of a real KSLV-II onboard equipment simulator.

A Study on Development of LCD monitor-Based Pilots' Ship-Handling Simulator

  • Jeong, Tae-Gweon;Chen, Chao;Lee, Shin-Geol;Lee, Jeong-Jin;Huh, Yong-Bum
    • Journal of Navigation and Port Research
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    • v.36 no.9
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    • pp.715-720
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    • 2012
  • This paper is to introduce the development of a LCD monitor-based pilots' ship handling simulator installed in the office of Korea Maritime Pilots Association. This simulator is composed of hardware which includes working server array, operation PC, monitor array, rudder, thruster and telegraph peripheral devices, and software which includes ship mathematical model software, ship conning software, image supporting software and so on. In this simulator, MMG mathematical model is used to create thirteen(13) ship models, which are based on sea trial data & pilots' opinion. According to requirements of pilots, virtual scenes of different port areas are built, and some required additional functions are also developed. By using this simulator, pilots can fulfill all kinds of training exercises, design of channel approaching ports, traffic safety analysis, prevention of accident research and other tasks, so as to grasp the characteristics of different ships, and accumulate experience for piloting.

Analysis of Diagnosis and Failsafe Algorithm Using Transmission Simulator (변속기 시뮬레이터를 이용한 진단 및 안전작동 알고리즘 분석)

  • Jung, Gyuhong
    • Transactions of the Korean Society of Automotive Engineers
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    • v.22 no.4
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    • pp.89-97
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    • 2014
  • As the digital control technologies in automotive industry have advanced, electronic control units(ECUs) play a key-role to improve system performance. Transmission control unit(TCU) is a shifting controller for automatic transmission of which major functions are to determine the shift and manage the shifting process considering the various sensor signal on transmission and driver's commands. As with any ECU in vehicle, TCU performs complex algorithms such as shift control, diagnostic and failsafe functions. However, firmware design analysis is hardly possible by the reverse engineering due to code protection. Transmission simulator is a hardware-in-the-loop simulator which enables TCU to work in normal mode by simulating the electrical signal of TCU interface. In this research, diagnosis and failsafe algorithm implemented on commercialized TCU is analyzed by using the transmission simulator that is developed for wheel loader construction vehicle. This paper gives various experimental results on the proportional solenoid current trajectories for different operating modes, error detection criterion and limphome mode gears for all the possible cases of clutch malfunction. The derived results for conventional TCU can be applied to the development of inherent TCU algorithms and the transmission simulator can also be utilized for the test of TCU to be developed.

Development of Integrated Orbit and Attitude Software-in-the-loop Simulator for Satellite Formation Flying

  • Park, Han-Earl;Park, Sang-Young;Park, Chandeok;Kim, Sung-Woo
    • Journal of Astronomy and Space Sciences
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    • v.30 no.1
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    • pp.1-10
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    • 2013
  • An integrated orbit and attitude control algorithm for satellite formation flying was developed, and an integrated orbit and attitude software-in-the-loop (SIL) simulator was also developed to test and verify the integrated control algorithm. The integrated algorithm includes state-dependent Riccati equation (SDRE) control algorithm and PD feedback control algorithm as orbit and attitude controller respectively and configures the two algorithms with an integrating effect. The integrated SIL simulator largely comprises an orbit SIL simulator for orbit determination and control, and attitude SIL simulator for attitude determination and control. The two SIL simulators were designed considering the performance and characteristics of related hardware-in-the-loop (HIL) simulators and were combined into the integrated SIL simulator. To verify the developed integrated SIL simulator with the integrated control algorithm, an orbit simulation and integrated orbit and attitude simulation were performed for a formation reconfiguration scenario using the orbit SIL simulator and the integrated SIL simulator, respectively. Then, the two simulation results were compared and analyzed with each other. As a result, the user satellite in both simulations achieved successful formation reconfiguration, and the results of the integrated simulation were closer to those of actual satellite than the orbit simulation. The integrated orbit and attitude control algorithm verified in this study enables us to perform more realistic orbit control for satellite formation flying. In addition, the integrated orbit and attitude SIL simulator is able to provide the environment of easy test and verification not only for the existing diverse orbit or attitude control algorithms but also for integrated orbit and attitude control algorithms.

Implementation of the Frame Memory Hardware for MPEG-2 Video Encoder (MPEG-2 비디오 부호화기의 프레임 메모리 하드웨어 구현)

  • 고영기;강의성;이경훈;고성제
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.24 no.9A
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    • pp.1442-1450
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    • 1999
  • In this paper, we present an efficient hardware architecture for the frame memory of the MPEG-2 video encoder. Both the total size of internal buffers and the number of logic gates are reduced by the proposed memory map which can provide an effective interface between MPEG-2 video encoder and the external DRAM. Furthermore, the proposed scheme can reduce the DRAM access time. To realize the frame memory hardware,$0.5\mu\textrm{m}$, VTI, vemn5a3 standard cell library is used. VHDL simulator and logic synthesis tool are used for hardware design and RTL (register transfer level) function verification. The frame memory hardware emulator of the proposed architecture is designed for gate-level function verification. It is expected that the proposed frame memory hardware using VHDL can achieve suitable performance for MPEG-2 MP@ML.

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Throughput Improvement and Power-Interruption Consideration of Fly-By-Wire Flight Control Computer (비행제어 컴퓨터의 Throughput 향상 및 Power-Interuption 대처 설계)

  • Lee, Cheol;Seo, Joon-Ho;Ham, Heung-Bin;Cho, In-Je;Woon, Hyung-Sik
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • v.35 no.10
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    • pp.940-947
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    • 2007
  • For the performance upgrade of a supersonic jet fighter, the processor and FLCC(Flight Control Computer) Architecture were upgraded from a baseline FLCC. Prior to the hardware implementation phase, the exact CPU throughput estimation is necessary. For this purpose, an experimental method for new FLCC throughput estimation was introduced in this study. While baseline FLCC operating, the CPU address bus was collected with logic analyzer, and then decoded to get the exact access times to each memory-memory and the number of program Instruction branches. Based on these data, a throughput test in CPU demo-board of the new FLCC configuration was performed. From test results, the CPU-Memory architecture was design-changed before FLCC hardware implementation phase. To check the flight stability degradation due to power-interrupt problem due to CPU-Memory architecture change, the piloted HILS (Hardware-In-the Loop Simulator) test was conducted.

Development of Hardware-in-the-Loop Simulator for Testing Embedded System of Automatic Transmission (자동변속기용 임베디드 시스템 성능 시험을 위한 Hardware-in-the Loop 시뮬레이터 구축)

  • Jang, In-Gyu;Seo, In-Keun;Jeon, Jae-Wook;Hwang, Sung-Ho
    • Journal of Institute of Control, Robotics and Systems
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    • v.14 no.3
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    • pp.301-306
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    • 2008
  • Drivers are becoming more fatigued and uncomfortable with increase in traffic density, and this condition can lead to slower reaction time. Consequently, they may face the danger of traffic accidents due to their inability to cope with frequent gear shifting. To reduce this risk, some drivers prefer automatic transmission (AT) over manual transmission (MT). The AT offers more superior drivability and less shifting shock than the MT; therefore, the AT market share has been increasing. The AT is controlled by an electronic control unit (ECU), which provides better shifting performance. The transmission control unit (TCU) is a higher-value-added product, so the companies that have advanced technologies end to evade technology transfer. With more cars gradually using the ECU, the TCU is expected to be faster and more efficient for organic communication and arithmetic processing between the control systems than the l6-bit controller. In this paper, the model of an automatic transmission vehicle using MATLAB/Simulink is developed for the Hardware in-the-Loop (HIL) simulation with a 32-bit embedded system, and also the AT control logic for shifting is developed by using MATLAB/Simulink. The developed AT control logic, transformed automatically by real time workshop toolbox, is loaded to a 32-bit embedded system platform based on Freescale's MPC565. With both vehicle model and 32-bit embedded system platform, we make the HIL simulation system and HIL simulation of AT based on real time operating system (RTOS) is performed. According to the simulation results, the developed HIL simulator will be used for the performance test of embedded system for AT with low cost and effort.

Research on the Main Memory Access Count According to the On-Chip Memory Size of an Artificial Neural Network (인공 신경망 가속기 온칩 메모리 크기에 따른 주메모리 접근 횟수 추정에 대한 연구)

  • Cho, Seok-Jae;Park, Sungkyung;Park, Chester Sungchung
    • Journal of IKEEE
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    • v.25 no.1
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    • pp.180-192
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    • 2021
  • One widely used algorithm for image recognition and pattern detection is the convolution neural network (CNN). To efficiently handle convolution operations, which account for the majority of computations in the CNN, we use hardware accelerators to improve the performance of CNN applications. In using these hardware accelerators, the CNN fetches data from the off-chip DRAM, as the massive computational volume of data makes it difficult to derive performance improvements only from memory inside the hardware accelerator. In other words, data communication between off-chip DRAM and memory inside the accelerator has a significant impact on the performance of CNN applications. In this paper, a simulator for the CNN is developed to analyze the main memory or DRAM access with respect to the size of the on-chip memory or global buffer inside the CNN accelerator. For AlexNet, one of the CNN architectures, when simulated with increasing the size of the global buffer, we found that the global buffer of size larger than 100kB has 0.8x as low a DRAM access count as the global buffer of size smaller than 100kB.

The development of full-scope replica simulator for variable supercritical pressure once-through fossil power plants (변압 관류형 초임계압 화력발전소 전범위 시뮬레이터 개발)

  • Lee, Jung-Kun;Ahn, Yeon-Shik;Jung, Hoon;Lee, Yong-Kwan;Han, Byoung-Sung
    • Journal of Institute of Control, Robotics and Systems
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    • v.4 no.3
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    • pp.392-399
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    • 1998
  • A full-scope replica type simulator whose MCR(main control room) has the same features and operation functions as MCR of the reference power plant has been developed for a fossil power plant. This simulator was developed with the model of Poryung Fossil Power Plant #3,4 which is the standard model of the Korean fossil power plant. It is the first localized simulator for the supercritical, variable boiler pressure type fossil power plant. The simulator provides various kinds of accidents which are in normal plant operation and thus enables operators to recover or reduce possible damages. To design and develop this kind of simulator, we need to integrate high technologies such as system analysis, plant operation and system integration of mechanics, physics, computer science. CASE(Computer Aided Software Engineering) tools were used to develop the dynamic model. This simulator will greatly contribute to the improvement of the safety and efficiency of the fossil power plant by implementing operator training. In this paper, the outline of software and hardware configuration and characteristics of the simulator are described, and the results of 30%, 50%, 75%, 100% load operation test will be discussed.

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