• Archives of design research
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• v.17 no.2
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• pp.413-424
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• 2004

This paper defines the telepresence as a particular type of experience, rather than a collection of hardware. Defining telepresence in this way provides a means for examining telepresence in relation to other types of mediated experience. Presence refers to the natural perception of an environment, and telepresence refers to the mediated perception of an environment. Factors influencing whether a particular mediated environment will induce a sense of telepresence include the following: the combination of sensory stimuli employed in the environment, the ways in which participants are able to interact with the environment, and the characteristics of the individual experiencing the environment. Telepresence art invites the people from remote worlds to networked cyber space and creates the experience of 'being there' by making participants control the virtual reality system and receive feedback from their teleactions. It is the way to produce an open and engaging experience that manifests the cultural changes brought about by remote control, remote vision, telekinesis, and real-time exchange of audiovisual information. The principal determinants of telepresence are sensory immersion, sensory fidelity, cognitive fidelity and personal factors. This paper applies the 4 determinants to telepresence art works such as Ken Goldberg's Telegarden, Monika Fleischmann & Wolfgang Strauss' The Home of the Brain, Paul Sermon's Telematic Dreaming, Telematic Vision, Eduardo Kac's Uriapuru, Simon Penny's Traces and Paul Sermon & Andrea Zapp's A Body of Water.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.12
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• pp.2202-2211
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• 2006

EXT3NS is a special-purpose file system for large scale multimedia streaming servers. It is built on top of streaming acceleration hardware device called Network-Storage card. The EXT3NS file system significantly improves streaming performance by eliminating memory-to-memory copy operations, i.e. sending video/audio from disk directly to network interface with no main memory buffering. In this paper, we design and implement a buffer cache mechanism, called PMEMCACHE, for EXT3NS file system. We also propose a buffer cache replacement method called ONS for the buffer cache mechanism. The ONS algorithm outperforms other existing buffer replacement algorithms in distributed multimedia streaming environment. In EXT3NS with PMEMCACHE, operation is 33MB/sec and random read operation is 2.4MB/sec. Also, the buffer replacement ONS algorithm shows better performance by 600KB/sec than other buffer cache replacement policies. As a result PMEMCACHE and an ONS can greatly improve the performance of multimedia steaming server which should supportmultiple client requests at the same time.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.9_10
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• pp.429-440
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• 2008

As embedded system becomes more complex, software development becomes more important in the entire design process. Most embedded applications consist of multi -tasks, that are executed in parallel. So, dataflow model that expresses concurrency naturally is preferred than sequential programming language to develop multitask software. For the execution of multitasking codes, operating system is essential to schedule multi-tasks and to deal with the communication between tasks. But, it is needed to execute multitasking code without as when the target hardware platform cannot execute as or target platforms are candidates of design space exploration, because it is very costly to port as for all candidate platforms of DSE. For this reason, we propose the serialized multitasking code generation technique from dataflow specification. In the proposed technique, a task is specified with dataflow model, and generated as a C code. Code generation consists of two steps: First, a block in a task is generated as a separate function. Second, generated functions are scheduled by a multitasking scheduler that is also generated automatically. To make it easy to write customized scheduler manually, the data structure and information of each task are defined. With the preliminary experiment of DivX player, it is confirmed that the generated code from the proposed framework is efficiently and correctly executed on the target system.

• International Journal of Contents
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• v.11 no.1
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• pp.41-51
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• 2015

Management systems for electronic library have been developed on the basis of Client/Server or ASP framework in domestic market for a long time. Therefore, both service provider and user suffer from their high cost and effort in management, maintenance, and repairing of software as well as hardware. Recently in addition, mobile devices like smartphone and tablet PC are frequently used as terminal devices to access computers through the Internet or other networks, sophisticatedly customized or personalized interface for n-screen service became more important issue these days. In this paper, we propose a new scheme of integrated management system for electronic library based on SaaS and Web Standard. We design and implement the proposed scheme applying Electronic Cabinet Guidelines for Web Standard and Universal Code System. Hosted application management style and software on demand style service models based on SaaS are basically applied to develop the management system. Moreover, a newly improved concept of duplication check algorithm in a hierarchical evaluation process is presented and a personalized interface based on web standard is applied to implement the system. Algorithms of duplication check for journal, volume/number, and paper are hierarchically presented with their logic flows. Total framework of our development obeys the standard feature of Electronic Cabinet Guidelines offered by Korea government so that we can accomplish standard of application software, quality improvement of total software, and reusability extension. Scope of our development includes core services of library automation system such as acquisition, list-up, loan-and-return, and their related services. We focus on interoperation compatibility between elementary sub-systems throughout complex network and structural features. Reanalyzing and standardizing each part of the system under the concept on the cloud of service, we construct an integrated development environment for generating, test, operation, and maintenance. Finally, performance analyses are performed about resource usability of server, memory amount used, and response time of server etc. As a result of measurements fulfilled over 5 times at different test points and using different data, the average response time is about 62.9 seconds for 100 clients, which takes about 0.629 seconds per client on the average. We can expect this result makes it possible to operate the system in real-time level proof. Resource usability and memory occupation are also good and moderate comparing to the conventional systems. As total verification tests, we present a simple proof to obey Electronic Cabinet Guidelines and a record of TTA authentication test for topics about SaaS maturity, performance, and application program features.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.3
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• pp.697-707
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• 2015

This paper covered the design and implementation of the demodulation receiver in the ADS-B 1090ES system, which is one of the CNS/ATM's surveillance systems. This researched demodulation performed at the level required by RTCA DO-268B and EUROCAE ED-129. The single signal process method, which applies a baseline multi-sample technique among multi-amplitude sample demodulations, was suggested to improve the quality of the receiver signal, the dynamic range and so on. The suggested multi-signal level tuning method has enhanced the single-signal process method, reducing the unstable reception ratio by the transmit output level difference and manufacturing receiver hardware. The result was that the receiver suggested by the method had 0~87dBm in dynamic range and -90dBm in MTL. This shows a better performance by -3dBm less than the international standard in ADS-B 1090ES ground receiver equipment. The systems which use a similar modulation method, will be considered to be widely applied.

• Journal of Satellite, Information and Communications
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• v.2 no.2
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• pp.22-28
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• 2007

Spectrum spreading, in its general form, can be conceived as an artificial expansion of the signal bandwidth with respect to the minimum Nyquist band required to transmit the desired information. Spreading can be functional to several objectives, including resilience to interference and jammers and reduction of power spectral density levels. In the paper, signal spreading is manly used for increasing the received energy, thus satisfying link budget constraints, for terminals with low aperture antennas, without increasing the transmitted EIRP. As a matter of fact, in many mobile scenarios, even when MODCOD configurations with very low spectral efficiency (i.e. QPSK-1/4) in DVB-S2 standard, are used, the link budget cannot be closed. Spectrum spreading has been recently proposed as a technique to improve system performance without introducing additional MODCOD configurations under the constraint of fixed power spectrum density level at the transmitter side. To this aim, the design of spectrum spreading techniques shall keep into consideration requirements such as spectrum mask, physical layer performance, link budget, hardware reuse, robustness, complexity, and backward compliance with existing commercial equipments. The proposed implementation allows to fully reuse the standard DVB-S2 circuitry and is inserted as an 'inner layer' in the standard DVB-S2 chain.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.60-67
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• 2008

A low-power 2.4GHz fractional-N frequency synthesizer has been designed for 2.4GHz ISM band applications such as Bluetooth, Zigbee, and WLAN. To achieve low-power characteristic, the design has been focused on the power optimization of power-hungry blocks such as VCO, prescaler, and ${\Sigma}-{\Delta}$ modulator. An NP-core type VCO is adopted to optimize both phase noise and power consumption. Dynamic D-F/Fs with no static DC current are employed in designing the low-power prescaler circuit. The ${\Sigma}-{\Delta}$ modulator is designed using a modulus mapping circuit for reducing hardware complexity and power consumption. The designed frequency synthesizer which was fabricated using a $0.18{\mu}m$ CMOS process consumes 7.9mA from a single 1.8V supply voltage. The experimental results show that a phase noise of -118dBc/Hz at 1MHz offset, the reference spur of -70dBc at 25MHz offset, and the channel switching time of $15{\mu}s$ over 25MHz transition have been achieved. The designed chip occupies an area of $1.16mm^2$ including pads where the core area is only $0.64mm^2$.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.12
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• pp.20-35
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• 2016

In this paper, in order to reduce the delay and area of the partial product accumulation (PPA) of the parallel decimal multiplier, a tree architecture that composed by multi-operand decimal CSAs and improved CLA is proposed. The proposed tree using multi-operand CSAs reduces the partial product quickly. Since the input range of the recoder of CSA is limited, CSA can get the simplest logic. In addition, using the multi-operand decimal CSAs to add decimal numbers that have limited range in specific locations of the specific architecture can reduce the partial products efficiently. Also, final BCD result can be received faster by improving the logic of the decimal CLA. In order to evaluate the performance of the proposed partial product accumulation, synthesis is implemented by using Design Complier with 180 nm COMS technology library. Synthesis results show the delay of the proposed partial product accumulation is reduced by 15.6% and area is reduced by 16.2% comparing with which uses general method. Also, the total delay and area are still reduced despite the delay and area of the CLA are increased.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.4
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• pp.15-25
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• 2012

The research on the FPGA CAD tools in academia has been lacking practicality due to the underlying FPGA fabric architecture which is too simple and inefficient to be applied for commercial FPGAs. Recently, the database of placement positions and routing graphs on commercial FPGA architectures has been built, and provided for enabling the academic development of placement and routing tools. To extend the limit of academic CAD tools even further, we have developed the evaluation toolkit for the K-FPGA architecture which is under development. By providing interface for exchanging data with a commercial FPGA toolkit at every step of mapping, packing, placement and routing in the tool chain, the toolkit enables individual tools to be developed without waiting for the results of the preceding step, and with no dependency on the quality of the results, and compared in detail with commercial tools at any step. Also, the fabric primitive library is developed by extracting the prototype from a reporting file of a commercial FPGA, restructuring it, and modeling the behavior of basic gates. This library can be used as the benchmarking target, and a reference design for new FPGA architectures. Since the architecture is described in a standard HDL which is familiar with hardware designers, and read in the tools rather than hard coded, the tools are "data-driven", and tolerable with the architectural changes due to the design space exploration. The experiments confirm that the developed library is correct, and the functional correctness of applications implemented on the FPGA fabric can be validated by simulation. The placement and routing tools are under development. The completion of the toolkit will enable the development of practical FPGA architectures which, in return, will synergically animate the research on optimization CAD tools.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.45 no.1
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• pp.41-49
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• 2008

Many machineries and equipments are being changing to various and complicated by development of recent technology and arrival of convergence age in distant future. These various and complicate equipments need more precise outcomes and low-power consumption sensors to get close and exact results. In this paper, we proposed fault tolerance and feedback theorem for sensor network and MEMS circuit which has a benefit of energy efficiency through wireless sensor network. The system is provided with independent sensor communication if possible as unused action, using idle condition of system and is proposed the least number of circuits. These technologies compared system efficiency after examining product of each Moving Distance by developed sensor which gives effects to execution of system witch is reduced things like control of management side and requirement for hardware, time, and interaction problems. This system is designed for practical application; however, it can be applied to a normal life and production environment such as "Ubiquitous City", "Factory Automata ion Process", and "Real-time Operating System", etc.