• The KIPS Transactions:PartB
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• v.10B no.5
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• pp.567-574
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• 2003

Application field of third dimension graphic is becoming diversification by the fast development of hardware recently. Various theory of details technology necessary to design game such as 3D MMORPG (Massive Multi-play Online Role Flaying Game) that do with third dimension. Cyber city should be absorbed. It is the detection speed that this treatise is necessary in game engine design. 3D MMORPG game engine has much factor that influence to speed as well as rendering processing because it express huge third dimension city´s grate many building and individual fast effectively by real time. This treatise nay get concept about the collision in 3D MMORPG and detection speed elevation of game engine through improved detection method. Space division is need to process fast dynamically wide outside that is 3D MMORPG´s main detection target. 3D is constructed with tree construct individual that need collision using processing geometry dataset that is given through new graph. We may search individual that need in collision detection and improve the collision detection speed as using hierarchical bounding box that use it with detection volume. Octree that will use by division octree is used mainly to express rightly static object but this paper use limited OSP by limited space division structure to use this in dynamic environment. Limited OSP space use limited space with method that divide square to classify typically complicated 3D space´s object. Through this detection, this paper propose follow contents, first, this detection may judge collision detection at early time without doing all polygon´s collision examination. Second, this paper may improve detection efficiency of game engine through and then reduce detection time because detection time of bounding box´s collision detection.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.4A
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• pp.336-344
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• 2005

Discrete Wavelet Transform(DWT) is the oncoming generation of compression technique that has been selected for MPEG4 and JEPG2000, because it has no blocking effects and efficiently determines frequency property of temporary time. In this paper, we propose an efficient bit-serial architecture for the low-power and low-complexity DWT filter, employing two-channel QMF(Qudracture Mirror Filter) PR(Perfect Reconstruction) lattice filter. The filter consists of four lattices(filter length=8) and we determine the quantization bit for the coefficients by the fixed-length PSNR(peak-signal-to-noise ratio) analysis and propose the architecture of the bit-serial multiplier with the fixed coefficient. The CSD encoding for the coefficients is adopted to minimize the number of non-zero bits, thus reduces the hardware complexity. The proposed folded 1D DWT architecture processes the other resolution levels during idle periods by decimations and its efficient scheduling is proposed. The proposed architecture requires only flip-flops and full-adders. The proposed architecture has been designed and verified by VerilogHDL and synthesized by Synopsys Design Compiler with a Hynix 0.35$\mu$m STD cell library. The maximum operating frequency is 200MHz and the throughput is 175Mbps with 16 clock latencies.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.11
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• pp.24-32
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• 2002

In this paper we implemented various image processing filtering using the format converter. This design method is based on realized the large processor-per-pixel array by integrated circuit technology. These two types of integrated structure are can be classify associative parallel processor and parallel process DRAM(or SRAM) cell. Layout pitch of one-bit-wide logic is identical memory cell pitch to array high density PEs in integrate structure. This format converter design has control path implementation efficiently, and can be utilize the high technology without complicated controller hardware. Sequence of array instruction are generated by host computer before process start, and instructions are saved on unit controller. Host computer is executed the pixel-parallel operation starting at saved instructions after processing start. As a result, we obtained three result that 1)simple smoothing suppresses higher spatial frequencies, reducing noise but also blurring edges, 2) a smoothing and segmentation process reduces noise while preserving sharp edges, and 3) median filtering, like smoothing and segmentation, may be applied to reduce image noise. Median filtering eliminates spikes while maintaining sharp edges and preserving monotonic variations in pixel values.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.171-174
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• 2005

According as marine leisure industry has developed and the demand of leisure culture has increased rapidly, a desire about service which supply marine safety and connect marine information is enlarging. The performance of personal mobile device has improved and been evolved by composition terminal. So, it became possible that storage and expression of multimedia information as well as simple communication facility. Domestic wireless internet has given development strain to developer and contents Provider(CP) because of different platform. And this has become hindrance factor of wireless internet activation. But, recently, the use of WIPI(Wireless Internet Platform for Interoperability), the wireless internet standard platform, could use different wireless application programs and also guarantee the independency for hardware. We wish to develop contents of download form that supply geographic information of Electronic Navigational Chart(ENC) in the marine that is digitalized to carrying along terminal of WIPI base and various informations for marine leisure. For this, DB that offer ENC and additional information should be constructed. Also, we need server (CPS; Contents provider Server) that offer required contents. In this paper, we design web retrieval agent which store request information to database. When consumer required necessary information through personal mobile device, CPS can inform that by real time. So, we wish to develop agent component that parse informations in various World Wide Webs, and store to database.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.9
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• pp.2109-2116
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• 2014

This paper presents the implementation and design of the advanced WI-FI systems with beam-forming antenna that radiate their power to the direction of user equipment to improve the overall throughput, contrast to the general WI-FI systems equipped with omni-antenna. The system consists of patch array antenna, DSP, FPGA, and Qualcomm's commercial chip. The beam-forming system on the FPGA utilizes the packet information from Qualcomm's commercial chip to control the phase shifters and attenuators of the patch array antenna. The PCI express interface has been used to maximize the communication speed between DSP and FPGA. The directions of arrival of users are managed using the database, and each user is distinguished by the MAC address given from the packet information. When the system wants to transmit a packet to one user, it forms beams to the direction of arrival of the corresponding user stored in the database to maximize the throughput. Directions of arrival of users are estimated using the received preamble in the packet to make its SINR as high as possible. The proposed beam-forming system was implemented using an FPGA and Qualcommm's commercial chip together. The implemented system showed considerable throughput improvement over the existing general AP system with omni-directional antenna in the multi-user communication environment.

• KIPS Transactions on Computer and Communication Systems
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• v.1 no.2
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• pp.71-78
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• 2012

The digital tachograph is a device that automatically records speed and distance of a vehicle, together with the driver's activity and vehicle status at an accident. It records vehicle speed, break status, acceleration, engine RPM, longitude and latitude of GPS, accumulated distance, and so on. European Commission regulation made digital tachographs mandatory for all trucks from 2005. Republic of Korea made digital tachographs mandatory for all new business vehicles from 2011 and is widening the range of vehicles that must install digital tachographs year by year. This device is used to analyze driver's daily driving information and car accidents. Under a car accident that makes the device reliability unpredictable, it is very important to store driving information with maximum reliability for its original mission. We designed and implemented a practical digital tachograph. This paper presents a storage scheme that consists of a first storage device with small capacity at a high reliability and a second storage device with large capacity at a low cost in order to reliably records data with a hardware at a low cost. The first storage device records data in a SLC NAND flash memory in a log-structured style. We present a reverse partial scan that overcomes the slow scan time of log-structured storages at the boot stage. The scheme reduced the scan time of the first storage device by 1/50. In addition, our design includes a scheme that fast stores data at a moment of accident by 1/20 of data transfer time of a normal method.

• Journal of Advanced Navigation Technology
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• v.25 no.5
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• pp.426-432
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• 2021

Continuous wave (CW) Doppler radar has the advantage of being able to solve the privacy problem unlike camera and obtains signals in a non-contact manner. Therefore, this paper proposes a human activity recognition (HAR) system using CW Doppler radar, and presents the hardware design and implementation results for acceleration. CW Doppler radar measures signals for continuous operation of human. In order to obtain a single motion spectrogram from continuous signals, an algorithm for counting the number of movements is proposed. In addition, in order to minimize the computational complexity and memory usage, binarized neural network (BNN) was used to classify human motions, and the accuracy of 94% was shown. To accelerate the complex operations of BNN, the FPGA-based BNN accelerator was designed and implemented. The proposed HAR system was implemented using 7,673 logics, 12,105 registers, 10,211 combinational ALUTs, and 18.7 Kb of block memory. As a result of performance evaluation, the operation speed was improved by 99.97% compared to the software implementation.

• 재활복지
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• v.18 no.4
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• pp.221-235
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• 2014

Recently, the frequency of stroke disease is increased due to the rapid aging population, and is contributed to the major occurrence factors of the posteriori acquired disability. This study is about an postural change device for the control of supine posture which is an assisted equipment using in daily rehabilitation process for overcoming the disability by the aftereffects of the stoke disease. In this paper, the existing domestic and Japan postural appliances is examined and its comparison and categorization is performed according to its functions and purposes. Here, in order to control the supine posture state, the design method for advanced multi functional system is proposed, which is devised to have an unified mattress control operations of combining the bedsore prevention tube with the supine posture tilting tube. And also, in addition of an smart function, it is designed to enable to perform an RF functions such as the monitoring of the present device state, the alteration of the basic position and the control of alternative floating and supine posture. This system control hardware consists of three main parts : the sensor detection part, the motor driving /control part, and the system control part for bluetooth communication. In results, we confirmed that the system designed by this research is possible to make it practical as an advanced smart postural change device combined by IoT technology in the application field of the recent IT technology.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.22 no.2
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• pp.201-211
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• 2012

This paper addresses a Full Disk Encryption hardware processor for SATA HDD in a single FPGA design, and shows its experimental result using an FPGA board. The proposed processor mainly consists of two blocks: the first block processes XTS-AES block cipher which is the IEEE P1619 standard of storage media encryption and the second block executes the interface between SATA Host (PC) and Device (HDD). To minimize the performance degradation, we designed the XTS-AES block with the 4-stage pipelined structure which can process a 128-bit block per 4 clock cycles and has 4.8Gbps (max) performance. Also, we implemented the proposed design with Xilinx ML507 FPGA board and our experiment showed 140MB/sec read/write speed in Windows XP 32-bit and a SATA II HDD. This performance is almost equivalent with the speed of the direct SATA connection without FDE devices, hence our proposed processor is very suitable for SATA HDD Full Disk Encryption environments.

• Journal of Advanced Navigation Technology
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• v.26 no.5
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• pp.365-372
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• 2022

Compared to sensors mainly used in human activity recognition (HAR) systems, inertial measurement unit (IMU) sensors are small and light, so can achieve lightweight system at low cost. Therefore, in this paper, we propose a binary neural network (BNN) based gait pattern analysis system using IMU sensor, and present the design and implementation results of an FPGA-based accelerator for computational acceleration. Six signals for gait are measured through IMU sensor, and a spectrogram is extracted using a short-time Fourier transform. In order to have a lightweight system with high accuracy, a BNN-based structure was used for gait pattern classification. It is designed as a hardware accelerator structure using FPGA for computation acceleration of binary neural network. The proposed gait pattern analysis system was implemented using 24,158 logics, 14,669 registers, and 13.687 KB of block memory, and it was confirmed that the operation was completed within 1.5 ms at the maximum operating frequency of 62.35 MHz and real-time operation was possible.