• Korean Journal of Computational Design and Engineering
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• v.8 no.2
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• pp.65-74
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• 2003

For virtual reality, virtual manufacturing system, or simulation based design, we need to visualize very large and complex 3D models which are comprising of very large number of polygons. To overcome the limited hardware performance and to attain smooth realtime visualization, there have been many researches about algorithms which reduce the number of polygons to be processed by graphics hardware. One of these algorithms, occlusion culling is a method of rejecting the objects which are not visible because they are occluded by other objects, and then passing only the visible objects to graphics hardware. Existing occlusion culling algorithms have some shortcomings such as the required long preprocessing time, the limitation of occluder shape, or the need for special hardware implementation. In this study, an efficient occlusion culling algorithm is proposed. The proposed algorithm reads and analyzes Z-buffer of graphics hardware using Microsoft DirectX, and then determines each object's visibility. This proposed algorithm can speed up visualization by reading Z-buffer using DirectX which can access hardware directly compared to OpenGL, by reading only the region to which each object is projected instead of reading the whole Z-Buffer, and the proposed algorithm can perform more exact visibility test by using simplified model instead of using bounding box. For evaluation, the proposed algorithm was applied to very large polygonal models. And smooth realtime visualization was attained.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.33 no.3
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• pp.437-447
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• 2023

Memory protection has been researched for decades for program execution protection. ARM recently developed a newhardware security feature to protect memory that was applied to real hardware. However, there are not many hardware withhardware memory protection feature and research has not been actively conducted yet. We perform diagnostics on howandhow it works on real hardware, and on security, with a new hardware memory protection feature, named 'Pointer Authentication Code'. Through this research, it will be possible to find out the direction, use, and security of future hardware security technologies and apply to the program.

• Journal of Broadcast Engineering
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• v.16 no.1
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• pp.54-63
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• 2011

This paper proposes a new equation to calculate computer-generated hologram (CGH) in a high speed and its cell-based VLSI (veri large scale integrated circuit) architecture. After finding the calculational regularity in the horizontal or vertical direction from the basic CGH equation, we induce the new equation to calculate the horizontal or vertical hologram pixel values in parallel. We also propose the architecture of the CGH cell consisting of a initial parameter calculator and update-phase calculator(s) on the basis of the equation and implement them in hardware. Also we show a hardware architecture to parallelize the calculation in the horizontal direction by extending CGH. In the experiments we analyze the used hardware resources. These analyses makes it possible to select the amount of hardware to the precision of the results. Here, for the CGH kernel and the structure of the processor, we used the platform from our previous works.

• Smart Media Journal
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• v.11 no.2
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• pp.70-76
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• 2022

IoT application development using a cloud server causes problems such as data transmission and reception delay, network traffic, and cost for real-time processing support in network connected hardware. To solve this problem, edge cloud-based platforms can use neuromorphic hardware to enable fast data transfer. In this paper, we propose a model optimization method for supporting spiking neural networks on FPGA hardware. We focused on auto-adjusting network model parameters optimized for neuromorphic hardware. The proposed method performs optimization to show higher performance based on user requirements for accuracy. As a result of performance analysis, it satisfies all requirements of accuracy and showed higher performance in terms of expected execution time, unlike the naive method supported by the existing open source framework.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.23 no.1
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• pp.59-68
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• 2009

Fuel cell generators as the distributed generation system with a few hundred watt$\sim$a few hundred kilowatt capacity, can supply the high quality electric power to user as compared with conventional large scale power plants. In this paper, PEMFC(polymer electrolyte membrane fuel cell) generator as micro-source is modelled by using PSIM simulation software and DSP based fuel cell hardware simulator based on the PSIM simulation model is implemented. The relation of fuel cell voltage and current(V-I curve) is linearized by first order function on the ohmic area in voltage-current curve of fuel cell. The implemented system is composed of a PEMFC hardware simulator, an isolated full bridge dc boost converter, and a 60[Hz] voltage source PWM inverter. The voltage-current-power(V-I-P) characteristics of the implemented fuel cell hardware simulator are verified in load variation and transient state and the 60[Hz] output voltage sinusoidal waveform of the PWM inverter is investigated under the resistance load and nonlinear diode load.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.4
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• pp.765-770
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• 2012

In this paper, we proposed an effective hardware structure using DCT-based inra-prediction mode selection to reduce computational complexity caused by intra mode decision. In this hardware structure, the input block is transformed at first and then analyzed to determine its texture directional tendency. the complexity has solved by performing intra prediction in only predicted edge direction. $4{\times}4$ DCT is calculated in one cycle using Multitransform_PE and Inta_pred_PE calculates one prediction mode in two cycles. Experimental results show that the proposed Intra prediction encoding needs only 517 cycles for one macroblock encoding. This architecture improves the performance by about 17% than previous designs. For hardware implementation, the proposed intra prediction encoder is implemented using Verilog HDL and synthesized with Megnachip $0.18{\mu}m$ standard cell library. The synthesis results show that the proposed architecture can run at 125MHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.229-232
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• 2012

This paper describes performance evaluation using fixed-point Matlab modeling and simulation, and hardware design of LDPC decoder which is based on Improved Normalized Min-Sum(INMS) decoding algorithm. The designed LDPC decoder supports 19 block lengths(576~2304) and 6 code rates(1/2, 2/3A, 2/3B, 3/4A, 3/4B, 5/6) of IEEE 802.16e mobile WiMAX standard. Considering hardware complexity, it is designed using a block-serial(partially parallel) architecture which is based on layered decoding scheme. A DFU based on sign-magnitude arithmetic is adopted to minimize hardware area. Hardware design is optimized by using INMS decoding algorithm whose performance is better than min-sum algorithm.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.40 no.3
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• pp.27-37
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• 2017

As the global uncertainty of manufacturing has increased and the quality problem has become global, the recall has become a fatal risk that determines the durability of the company. In addition, as the convergence of PSS (product-service system) product becomes common due to the development of IT convergence technology, if the function of any part of hardware or software does not operate normally, there will be a problem in the entire function of PSS product. In order to manage the quality of such PSS products in a stable manner, a new approaches is needed to analyze and manage the hardware and software parts at the same time. However, the Fishbone diagram, FTA, and FMEA, which are widely used to interpret the current quality problem, are not suitable for analyzing the quality problem by considering the hardware and software at the same time. In this paper, a quality risk assessment model combining FTA and FMEA based on defect rate to be assessed daily on site to manage quality and fishbone diagram used in group activity to solve defective problem. The proposed FTA-FMEA based risk assessment model considers the system structure characteristics of the defect factors in terms of the relationship between hardware and software, and further recognizes and manages them as risk. In order to evaluate the proposed model, we applied the functions of ITS (intelligent transportation system). It is expected that the proposed model will be more effective in assessing quality risks of PSS products because it evaluates the structural characteristics of products and causes of defects considering hardware and software together.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.3A
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• pp.185-196
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• 2009

SCA is proposed in order to operate various wireless systems in the single terminal platforms and uses the CORBA middleware to guarantee the platform-independence for software components. As the reconstruction demand is expanded in the software component to the logic level to many reasons, CORBA has to guarantee the independence of hardware on board. Accordingly. the characteristics depending on hardware board is ed. And the IDL-based interworking interface about the component has to be provided. In this paper, we described about local transport for guaranteeing the independency on the hardware board and the HAO Core for providing a coupling by the CORBA IDL identically with the other component. HAO produced at 2,900 logic cell size in average and provided the performance of the tens times than the software component. Through the use of HAO in the SCA-based development environment, it was naturally expanded to not only the software area but also the FPGA logic.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.12
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• pp.1688-1696
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• 2020

The paradigm of Internet-of-things(IoT) systems is changing from a cloud-based system to an edge-based system to solve delays caused by network congestion, server overload and security issues due to data transmission. However, edge-based IoT systems have fatal weaknesses such as lack of performance and flexibility due to various limitations. To improve performance, application-specific hardware can be implemented in the edge device, but performance cannot be improved except for specific applications due to a fixed function. This paper introduces a edge-centric metamorphic IoT(mIoT) platform that can use a variety of hardware through on-demand partial reconfiguration despite the limited hardware resources of the edge device, so we can increase the performance and flexibility of the edge device. According to the experimental results, the edge-centric mIoT platform that executes the reconfiguration algorithm at the edge was able to reduce the number of server accesses by up to 82.2% compared to previous studies in which the reconfiguration algorithm was executed on the server.