• ETRI Journal
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• v.34 no.1
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• pp.76-86
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• 2012

The block cipher ARIA has been threatened by side-channel analysis, and much research on countermeasures of this attack has also been produced. However, studies on countermeasures of ARIA are focused on software implementation, and there are no reports about hardware designs and their performance evaluation. Therefore, this article presents an advanced masking algorithm which is strong against second-order differential power analysis (SODPA) and implements a secure ARIA hardware. As there is no comparable report, the proposed masking algorithm used in our hardware module is evaluated using a comparison result of software implementations. Furthermore, we implement the proposed algorithm in three types of hardware architectures and compare them. The smallest module is 10,740 gates in size and consumes an average of 47.47 ${\mu}W$ in power consumption. Finally, we make ASIC chips with the proposed design, and then perform security verification. As a result, the proposed module is small, energy efficient, and secure against SODPA.

• Journal of IKEEE
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• v.24 no.2
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• pp.502-506
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• 2020

With the development of autonomous driving technology, the importance of object recognition technology is increasing. Haze removal is required because the hazy weather reduces visibility and detectability in object recognition. However, the image from which the haze has been removed cannot properly reflect the unique color, and a detection error occurs. In this paper, we use CIE1931 color coordinate system to extend or reduce the color area to provide algorithms and hardware that reflect the colors of the real world. In addition, we will implement hardware capable of real-time processing in a 4K environment as the image media develops. This hardware was written in Verilog and implemented on the SoC verification board.

• Journal of Platform Technology
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• v.6 no.4
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• pp.26-33
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• 2018

In this paper, we propose an image retrieval algorithm for real-time processing and design it as hardware. The proposed method is based on the classification of BoWs(Bag of Words) algorithm and proposes an image search algorithm using bit stream. K-fold cross validation is used for the verification of the algorithm. Data is classified into seven classes, each class has seven images and a total of 49 images are tested. The test has two kinds of accuracy measurement and speed measurement. The accuracy of the image classification was 86.2% for the BoWs algorithm and 83.7% the proposed hardware-accelerated software implementation algorithm, and the BoWs algorithm was 2.5% higher. The image retrieval processing speed of BoWs is 7.89s and our algorithm is 1.55s. Our algorithm is 5.09 times faster than BoWs algorithm. The algorithm is largely divided into software and hardware parts. In the software structure, C-language is used. The Scale Invariant Feature Transform algorithm is used to extract feature points that are invariant to size and rotation from the image. Bit streams are generated from the extracted feature point. In the hardware architecture, the proposed image retrieval algorithm is written in Verilog HDL and designed and verified by FPGA and Design Compiler. The generated bit streams are stored, the clustering step is performed, and a searcher image databases or an input image databases are generated and matched. Using the proposed algorithm, we can improve convenience and satisfaction of the user in terms of speed if we search using database matching method which represents each object.

• Journal of Institute of Control, Robotics and Systems
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• v.16 no.9
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• pp.905-912
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• 2010

Modern version of advanced supersonic fighter have ATCS (Automatic Thrust Control System) to maximum flight safety, fuel efficiency and mission capability the integrated advanced autopilot system such as TFS (Terrain Following System), GCAS (Ground Collision Avoidance System) and AARS (Automatic Attitude Recovery System) and etc. This paper addresses the design and verification of ATCS based on advanced supersonic trainer in HILS (Hardware In the Loop Simulator) with minimum hardware modification to reduce of development cost and maintain of system reliability. The function of ATCS is consisted of target speed hold mode in UA (Up and Away) and angle of attack hold mode in PA (Power Approach). The real-time pilot evaluation reveals that pilot workload is minimized in cruise and approach flight stage by ATCS.

• Bulletin of the Korean Space Science Society
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• 2011.04a
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• pp.32.2-32.2
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• 2011

State dependent Riccati equation (SDRE) control technique has been widely used in the control society. Although it solves nonlinear optimal control problems, which minimizes state error and control efforts simultaneously, it has drawbacks when it is to be applied to the real time systems in that it requires much computational efforts. So the real time system whose computational ability is limited (for example, satellites) cannot afford to use SDRE controller. To solve this problem, a hybrid controller which is based on MSDRE (Modified SDRE) and ANFIS (Adaptive Neuro-Fuzzy Inference System) has been proposed by Abdelrahman et al. (2010). We propose a hybrid controller based on SDRE and ANFIS, and apply the hybrid controller to the hardware attitude simulator to perform a HIL (Hardware-In-the-Loop) simulation. Through HIL simulation, it is demonstrated that the hybrid controller satisfies the control requirement and the computation load is reduced significantly. In addition, the effects of statistical properties of the ANFIS training data to the performance of the ANFIS controller have been analyzed.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.1
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• pp.263-267
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• 2011

This paper analyzed randomness characteristics of output data in generator based on hardware noise source. Also it is enhanced security randomness in the output stream of generator, which is applied on Laplacian filter. First it reviews criteria of randomness verification of output stream of hardware noise generator, and presents the enhanced results of output stream of generator, which is applied on Laplacian filter.

• Journal of the Korean Society for Railway
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• v.5 no.3
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• pp.158-166
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• 2002

In this paper, we introduce the software and hardware of the measurement system for on-line testing and evaluation of high speed railway. The test items focus on the verification of the performance and acquirement of the technical data of the high speed railway system. The software controls the hardware of the measurement system, perform the analysis and calculation of measurement data and acts as interface between users and the system hardware. For this purpose, three programs a measuring program, a monitoring program and post-processing program are developed. The detailed test scenario is in the process of development to closely follow the process of development and design of the system.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.781-782
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• 2006

This treatise proposed environment for Embedded system's development. Virtual platform can help to solve problem that hardware designer can experience at design process of hardware. Compose circuit of most suitable that is verified before mix parts by various kinds method and compose circuit by board level because can do simulation with software and software that is optimized to hardware and offer flexibility that can test. Therefore, can shorten expense that is cost in development and time. Embody development platform for 8051 systems for verification of development platform, and compose and verified system in various kinds structure.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.852-855
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• 2003

This paper reports the RFC(Recursive Flow Classification) algorithm that is available on multiple fields. It is easy to be implemented by both software and hardware. For high speed classification of packets, the implementation of RFC is essential by hardware. Hence, in this paper, RFC algorithm is simulated by Verilog-HDL, and it verify the efficiency of the algorithm. The result shows that the algorithm can perform a packet classification within several cycles. It is not only much faster than software implementation but also enough to support OC192c.

• Electronics and Telecommunications Trends
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• v.36 no.6
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• pp.67-77
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• 2021

Since Richard Feynman presented the concept of quantum computers, quantum computing have been identified today overcoming the limits of supercomputing in various applications. Quantum hardware has steadily developed into 50 to hundreds of qubits of various quantum hardware technologies based on superconductors, semiconductors, and trapped ions over 40 years. However, it is possible to use a NISQ (Noisy Intermediate Scale Quantum) level quantum device that currently has hardware constraints. In addition, the software environment in which quantum algorithms for problem solving in various applications can be executed is pursuing research with quantum computing software such as programming language, compiler, control, testing and verification. The development of quantum software is essential amid intensifying technological competition for the commercialization of quantum computers. Therefore, this paper introduces the trends of the latest technology, focusing on quantum computing software platforms, and examines important software component technologies.