• Title/Summary/Keyword: Hardware Verification

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Hand Tracking and Calibration Algorithm Using the EPIC Sensors (EPIC 센서를 이용한 Hand Tracking 및 Calibration 알고리즘)

  • Jo, Jung Jae;Kim, Young Chul
    • Smart Media Journal
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    • v.2 no.1
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    • pp.27-30
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    • 2013
  • In this paper, we research the hand tracking and calibration algorithm using the EPIC sensor. We analyze the characteristics of EPIC sensor to be more sensitive in the around E-filed, and then we implement the 2-dimensional axis-transformation using the difference of detected amplitude between EPIC sensors. In addition, we implement the calibration algorithm considering the characteristics of EPIC sensor, and then we apply the Kalman filter to efficiently track a target. Thus, we implement the environment of window applications for verification and analysis the implemented algorithm. In turn, we use the DAQ API to extract the analog data. The DAQ hardware has the function of measuring and generating an electrical signal. Moreover, we confirm the movement of mouse cursor by detecting the potential difference depending on the movement of the user's hands.

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Analysis of the MSC(Multi-Spectral Camera) Operational Parameters

  • Yong, Sang-Soon;Kong, Jong-Pil;Heo, Haeng-Pal;Kim, Young-Sun
    • Korean Journal of Remote Sensing
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    • v.18 no.1
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    • pp.53-59
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    • 2002
  • The MSC is a payload on the KOMPSAT-2 satellite to perform the earth remote sensing. The instrument images the earth using a push-broom motion with a swath width of 15 km and a GSD(Ground Sample Distance) of 1 m over the entire FOV(Field Of View) at altitude 685 km. The instrument is designed to haute an on-orbit operation duty cycle of 20% over the mission lifetime of 3 years with the functions of programmable gain/offset and on-board image data compression/storage. The MSC instrument has one channel for panchromatic imaging and four channel for multi-spectral imaging covering the spectral range from 450nm to 900nm using TDI(Time Belayed Integration) CCD(Charge Coupled Device) FPA(Focal Plane Assembly). The MSC hardware consists of three subsystem, EOS(Electro Optic camera Subsystem), PMU(Payload Management Unit) and PDTS(Payload Data Transmission Subsystem) and each subsystems are currently under development and will be integrated and verified through functional and space environment tests. Final verified MSC will be delivered to spacecraft bus for AIT(Assembly, Integration and Test) and then COMSAT-2 satellite will be launched after verification process through IST(Integrated Satellite Test). In this paper, the introduction of MSC, the configuration of MSC electronics including electrical interlace and design of CEU(Camera Electronic Unit) in EOS are described. MSC Operation parameters induced from the operation concept are discussed and analyzed to find the influence of system for on-orbit operation in future.

Development and Analysis of Low Cost Telecommand Processing System for Domestic Development Satellites (국내 개발 인공위성을 위한 저비용 원격명령 처리 시스템 구현 및 분석)

  • Park, Sang-Seob;Lee, Seongjin;Jun, Yong-Kee
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • v.49 no.6
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    • pp.481-488
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    • 2021
  • The satellite telecommand processing system is the only way to provide telecommands for status monitoring, control, and mission execution. Domestic satellites can be divided into science, technology, and multi-purpose satellites, and geostationary satellites. These Satellites uses CCSDS standard protocol to communicate with ground stations. However, existing domestic satellites use only software to decode telecommands which increases cost of software development and verification of the developed software. Performance of software only approach is relatively low compared to hardware. In this paper, we present ASIC processing system specifically designed to decode telecommands. The system consists of a telecommand RAM, a protocol RAM/ROM, an ASIC, an interface unit of FPGA, and a relay block. The system handles general commands and pulse commands that are used in satellites. We established a ground station equipment and test environment to verify the system functionality, The result shows that our system reduces the development cost by 1/5 and improves the performance by 105 times compared to the previous systems that decode telecommands only by software.

Performance analysis and verification of underwater acoustic communication simulator in medium long-range multiuser environment (중장거리 다중송신채널 환경에서 수중음향통신 시뮬레이터 성능 분석 및 검증)

  • Park, Heejin;Kim, Donghyeon;Kim, J.S.;Song, Hee-Chun;Hahn, Joo Young
    • The Journal of the Acoustical Society of Korea
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    • v.37 no.6
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    • pp.451-456
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    • 2018
  • UAComm (Underwater Acoustic Communication) is an active research area, and many experiment has been performed to develop UAComm system. In this paper, we investigate the possibility of modifying and applying VirTEX (Virtual Time series EXperiment) to medium long range MIMO (Multiple-Input Multiple-Output) UAComm of about 20 km range for the analysis and performance prediction of UAComm system. Since VirTEX is a time-domain simulator, the generated time series can be used in HILS (Hardware In the Loop Simulation) to develop UAComm system. The developed package is verified through comparing with the sea-going FAF05 (Focused Acoustic Field 2005) experimental data. The developed simulator can be used to predict the performance of UAComm system, and even replace the expensive sea-going experiment.

Design and Implementation of Hand Gesture Recognizer Based on Artificial Neural Network (인공신경망 기반 손동작 인식기의 설계 및 구현)

  • Kim, Minwoo;Jeong, Woojae;Cho, Jaechan;Jung, Yunho
    • Journal of Advanced Navigation Technology
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    • v.22 no.6
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    • pp.675-680
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    • 2018
  • In this paper, we propose a hand gesture recognizer using restricted coulomb energy (RCE) neural network, and present hardware implementation results for real-time learning and recognition. Since RCE-NN has a flexible network architecture and real-time learning process with low complexity, it is suitable for hand recognition applications. The 3D number dataset was created using an FPGA-based test platform and the designed hand gesture recognizer showed 98.8% recognition accuracy for the 3D number dataset. The proposed hand gesture recognizer is implemented in Intel-Altera cyclone IV FPGA and confirmed that it can be implemented with 26,702 logic elements and 258Kbit memory. In addition, real-time learning and recognition verification were performed at an operating frequency of 70MHz.

Chaincode-based File Integrity Verification Model (체인코드 기반의 파일 무결성 검증 모델)

  • Kim, Hyo-Jong;Han, Kun-Hee;Shin, Seung-Soo
    • Journal of the Korea Convergence Society
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    • v.12 no.4
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    • pp.51-60
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    • 2021
  • Recent advances in network and hardware technologies have led to active research and multiple network technologies that fuse blockchain technologies with security. We propose a system model that analyzes technologies using existing blockchain and verifies the integrity of files using private blockchain in a limited environment. The proposed model can be written as a chain code of Hyperleisure Fabric, a private blockchain platform, and verified for integrity of files through Hyperleisure Explorer, a private blockchain integrated management platform. The system performance of the proposed model was analyzed from a developer perspective and from a user perspective. As a result of the analysis, there are compatibility problems according to the version of various modules to run the blockchain platform, and only limited elements such as chain code status and groups can be checked.

Design of Efficient NTT-based Polynomial Multiplier (NTT 기반의 효율적인 다항식 곱셈기 설계)

  • Lee, SeungHo;Lee, DongChan;Kim, Yongmin
    • Journal of IKEEE
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    • v.25 no.1
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    • pp.88-94
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    • 2021
  • Public-key cryptographic algorithms such as RSA and ECC, which are currently in use, have used mathematical problems that would take a long time to calculate with current computers for encryption. But those algorithms can be easily broken by the Shor algorithm using the quantum computer. Lattice-based cryptography is proposed as new public-key encryption for the post-quantum era. This cryptographic algorithm is performed in the Polynomial Ring, and polynomial multiplication requires the most processing time. Therefore, a hardware model module is needed to calculate polynomial multiplication faster. Number Theoretic Transform, which called NTT, is the FFT performed in the finite field. The logic verification was performed using HDL, and the proposed design at the transistor level using Hspice was compared and analyzed to see how much improvement in delay time and power consumption was achieved. In the proposed design, the average delay was improved by 30% and the power consumption was reduced by more than 8%.

A Secure Maintenance Scheme of Secret Data on Trusted Mobile Platform Environment (Trusted Mobile Platform 환경에서의 안전한 비밀 데이터 유지(이전) 방안)

  • Kang, Dong-Wan;Lee, Im-Yeong;Han, Jin-Hee;Jun, Sung-Ik
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.18 no.4
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    • pp.79-91
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    • 2008
  • Modern society as an information society, a lot of information is communicated in on-line. Specially, mobile environment based on radio communication has a characteristic of flexibility compared with wire communication and is developed rapidly. However, the more mobile technology is developed the more security for sensitive information is needed. Therefore, MTM(Mobile Trusted Module) is developed and promoted by TCG(Trusted Computing Group), which is an industry standard body to enhance the security level in the mobile computing environment. MTM, hardware security module for mobile environment, offers user's privacy protection, platform integrity verification, and individual platform attestation. On the other hand, secure migration scheme is required in case secret data or key is transferred from one platform to the other platform. In this paper, we analyze migration schemes which were described in TCG standard and other papers and then propose security maintenance scheme for secret data using USIM(Universal Subscriber Identity Module).

Torque Ripple Reduction Method With Enhanced Efficiency of Multi-phase BLDC Motor Drive Systems Under Open Fault Conditions (다상 BLDC 모터 드라이브 시스템의 개방 고장 시 효율 향상이 고려된 토크 리플 저감 대책)

  • Kim, Tae-Yun;Suh, Yong-Sug;Park, Hyeon-Cheol
    • The Transactions of the Korean Institute of Power Electronics
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    • v.27 no.1
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    • pp.33-39
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    • 2022
  • A multi-phase brushless direct current (BLDC) motor is widely used in large-capacity electric propulsion systems such as submarines and electric ships. In particular, in the field of military submarines, the polyphaser motor must suppress torque ripple in various failure situations to reduce noise and ensure stable operation for a long time. In this paper, we propose a polyphaser current control method that can improve efficiency and reduce torque ripple by minimizing the increase in stator winding loss at maximum output torque by controlling the phase angle and amplitude of the steady-state current during open circuit failure of the stator winding. The proposed control method controls the magnitude and phase angle of the healthy phase current, excluding the faulty phase, to compensate for the torque ripple that occurs in the case of a phase open failure of the motor. The magnitude and phase angle of the controlled steady-state current are calculated for each phase so that copper loss increase is minimized. The proposed control method was verified using hardware-in-the-loop simulation (HILS) of a 12-phase BLDC motor. HILS verification confirmed that the increase in the loss of the stator winding and the magnitude of the torque ripple decreased compared with the open phase fault of the motor.

A Reconfigurable Integration Test and Simulation Bed for Engagement Control Using Virtualization (가상화 기반의 재구성 용이한 교전통제 통합시험시뮬레이션 베드)

  • Kilseok Cho;Ohkyun Jeong;Moonhyung Yoon
    • Journal of the Korea Institute of Military Science and Technology
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    • v.26 no.1
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    • pp.91-101
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    • 2023
  • Modeling and Simulation(M&S) technology has been widely used to solve constraints such as time, space, safety, and cost when we implement the same development and test environments as real warfare environments to develop, test, and evaluate weapon systems for the last several decades. The integration and test environments employed for development and test & evaluation are required to provide Live Virtual Construction(LVC) simulation environments for carrying out requirement analysis, design, integration, test and verification. Additionally, they are needed to provide computing environments which are possible to reconfigure computing resources and software components easily according to test configuration changes, and to run legacy software components independently on specific hardware and software environments. In this paper, an Integration Test and Simulation for Engagement Control(ITSEC) bed using a bare-metal virtualization mechanism is proposed to meet the above test and simulation requirements, and it is applied and implemented for an air missile defense system. The engagement simulation experiment results conducted on air and missile defense environments demonstrate that the proposed bed is a sufficiently cost-effective and feasible solution to reconfigure and expand application software and computing resources in accordance with various integration and test environments.