• Title/Summary/Keyword: Hardware Trojan Horse

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Trends of Hardware-based Trojan Detection Technologies (하드웨어 트로이목마 탐지기술 동향)

  • Choi, Y.S.;Lee, S.S.;Choi, Y.J.;Kim, D.W.;Choi, B.C.
    • Electronics and Telecommunications Trends
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    • v.36 no.6
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    • pp.78-87
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    • 2021
  • Information technology (IT) has been applied to various fields, and currently, IT devices and systems are used in very important areas, such as aviation, industry, and national defense. Such devices and systems are subject to various types of malicious attacks, which can be software or hardware based. Compared to software-based attacks, hardware-based attacks are known to be much more difficult to detect. A hardware Trojan horse is a representative example of hardware-based attacks. A hardware Trojan horse attack inserts a circuit into an IC chip. The inserted circuit performs malicious actions, such as causing a system malfunction or leaking important information. This has increased the potential for attack in the current supply chain environment, which is jointly developed by various companies. In this paper, we discuss the future direction of research by introducing attack cases, the characteristics of hardware Trojan horses, and countermeasure trends.

Run-Time Hardware Trojans Detection Using On-Chip Bus for System-on-Chip Design (온칩버스를 이용한 런타임 하드웨어 트로이 목마 검출 SoC 설계)

  • Kanda, Guard;Park, Seungyong;Ryoo, Kwangki
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.20 no.2
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    • pp.343-350
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    • 2016
  • A secure and effective on-chip bus for detecting and preventing malicious attacks by infected IPs is presented in this paper. Most system inter-connects (on-chip bus) are vulnerable to hardware Trojan (Malware) attack because all data and control signals are routed. A proposed secure bus with modifications in arbitration, address decoding, and wrapping for bus master and slaves is designed using the Advanced High-Performance and Advance Peripheral Bus (AHB and APB Bus). It is implemented with the concept that arbiter checks share of masters and manage infected masters and slaves in every transaction. The proposed hardware is designed with the Xilinx 14.7 ISE and verified using the HBE-SoC-IPD test board equipped with Virtex4 XC4VLX80 FPGA device. The design has a total gate count of 39K at an operating frequency of 313MHz using the $0.13{\mu}m$ TSMC process.