• International Journal of Fuzzy Logic and Intelligent Systems
• /
• v.5 no.3
• /
• pp.206-215
• /
• 2005

In this paper, we propose a new design method of Genetic Algorithm Processor(GAP) and Evolvable Hardware(EHW). All sorts of creature evolve its structure or shape in order to adapt itself to environments. Evolutionary Computation based on the process of natural selection not only searches the quasi-optimal solution through the evolution process, but also changes the structure to get best results. On the other hand, Genetic Algorithm(GA) is good fur finding solutions of complex optimization problems. However, it has a major drawback, which is its slow execution speed when is implemented in software of a conventional computer. Parallel processing has been one approach to overcome the speed problem of GA. In a point of view of GA, long bit string length caused the system of GA to spend much time that clear up the problem. Evolvable Hardware refers to the automation of electronic circuit design through artificial evolution, and is currently increased with the interested topic in a research domain and an engineering methodology. The studies of EHW generally use the XC6200 of Xilinx. The structure of XC6200 can configure with gate unit. Each unit has connected up, down, right and left cell. But the products can't use because had sterilized. So this paper uses Vertex-E (XCV2000E). The cell of FPGA is made up of Configuration Logic Block (CLB) and can't reconfigure with gate unit. This paper uses Vertex-E is composed of the component as cell of XC6200 cell in VertexE

• Journal of KIISE:Computer Systems and Theory
• /
• v.29 no.7
• /
• pp.422-430
• /
• 2002

For a time-multiplexed FPGA, a circuit is partitioned into several subcircuits, so that they temporally share the same physical FPGA device by hardware reconfiguration. In these architectures, all the hardware reconfiguration information called contexts are generated and downloaded into the chip, and then the pre-scheduled context switches occur properly and timely. Since the maximum number of the LUT's required in the same time determines the size of the chip used in the synthesis, it needs to be minimized, if possible. Many previous work use their own approaches, which are very similar to either scheduling method in high level synthesis or multi-way circuit partitioning method, to solve the problem. In this paper, we propose a method which estimates the lower bound on the number of LUT's without performing any actual synthesis. The estimated lower bounds help to evaluate the results of the previous work. If the estimated lower bound on the number of LUT's exactly matches the number of LUT's of the result from the previous work, the result must be optimal. In contrast, if they do not match, the following two cases are expected : the more exact lower bound may exist, or we might find the new synthesis result better than the result from the previous work. Experimental results show that our lower bound estimation method is very accurate. In almost al] cases experimented, the estimated lower bounds on the number of LUT's exactly match those of the previous synthesis results respectively, implying that the best results from the previous work are optimal as well as our method predicted the exact lower bound for those examples.

• Speech Sciences
• /
• v.11 no.2
• /
• pp.181-192
• /
• 2004

This paper presents an efficient speech interactive agent rendering smooth car navigation and Telematics services, by employing embedded automatic speech recognition (ASR), distributed speech recognition (DSR) and text-to-speech (ITS) modules, all while enabling safe driving. A speech interactive agent is essentially a conversational tool providing command and control functions to drivers such' as enabling navigation task, audio/video manipulation, and E-commerce services through natural voice/response interactions between user and interface. While the benefits of automatic speech recognition and speech synthesizer have become well known, involved hardware resources are often limited and internal communication protocols are complex to achieve real time responses. As a result, performance degradation always exists in the embedded H/W system. To implement the speech interactive agent to accommodate the demands of user commands in real time, we propose to optimize the hardware dependent architectural codes for speed-up. In particular, we propose to provide a composite solution through memory reconfiguration and efficient arithmetic operation conversion, as well as invoking an effective out-of-vocabulary rejection algorithm, all made suitable for system operation under limited resources.

• Journal of the Korea Society of Computer and Information
• /
• v.11 no.2 s.40
• /
• pp.35-42
• /
• 2006

In this paper we implement a new simulator for performance analysis of a parallel digital signal processing distributed shared memory multiprocessor systems. using Parsec The key idea of this simulator is suitable in simulation of system that uses DMA function of TMS320C6701 DSP chip and local memory which have fast access time. Also, because correction of performance parameter and reconfiguration for hardware components are easy, we can analyze performance of system in various execution environments. In the simulation, FET, 2D FET, Matrix Multiplication. and Fir Filter, which are widely used DSP algorithms. have been employed. Using our simulator, the result has been recorded according to different the number of processor, data sizes, and a change of hardware element. The performance of our simulator has been verified by comparing those recorded results.

• Journal of KIISE:Computing Practices and Letters
• /
• v.16 no.11
• /
• pp.1051-1055
• /
• 2010

Software defined radio(SDR) technology implements wireless communication protocols as software instead of dedicated hardware. SDR enables reconfiguration of wireless communication protocols without expensive hardware modification. However, as the SDR systems are equipped with additional programmable processors, they suffer significant power dissipation. This paper proposes a novel power management technique for SDR systems, called the combined modulation and voltage scaling (CMVS). Numerical analyses were performed to evaluate the effectiveness of CMVS. The results show that CMVS minimizes power dissipation while satisfying the given data transfer rate.

• 제어로봇시스템학회:학술대회논문집
• /
• 2005.06a
• /
• pp.1123-1126
• /
• 2005

This paper introduces the key features of NCS (Network based Control System), which is quite a new concept in the industrial automation market. Two control systems "DCS" and "PLC" have been recognized as control systems used for process and factory automation during the past decades. However, the market requires more complex functionality, such as monitoring and operation, alarm handling and notification from remote locations using the Web or e-mail. Besides enhancing functionality, interoperability between each device and system is highly required since network and engineering tools provided by many vendors do not cooperate with each others, so that lots of conversion, reconfiguration and reprogramming are required when expanding systems. NCS can meet this requirement, installing leading-edged IT technology using international standards for network and engineering environment. NCS, which is a harmony of web functionality, networkability and a reliable control function, enables information integration and responding to the market's requirements with agility and high reliability.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.5 no.4
• /
• pp.243-248
• /
• 2005

The UAV (Unmanned Aerial Vehicle) systems like unmanned autonomous helicopters are used in various missions of flight navigation and used to collect the environmental information of the surroundings. To realize the full functionalities of the UAV, the software part becomes a challenging problem. In this paper embedded real-time software architecture for unmanned autonomous helicopter is proposed that guarantee real-time performance of hard-real time tasks and re-configurability of soft-real time and non-real time tasks. The proposed software architecture has four layers: hardware, execution, service agent and remote user interface layer according to the reactiveness level for external events. In addition, the layered separation of concurrent tasks makes different kinds of mission reconfiguration possible in the system. An Unmanned autonomous helicopter system was implemented (Kyosho RC Helicopter) in our lab to test and evaluate the performance of the proposed system.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
• /
• v.2
• /
• pp.347-352
• /
• 2006

Narrowband interference can severely degrade the performance of GPS receivers. Detecting the presence of interference and then characterizing it can lead to its removal. Receivers can be reconfigured to focus on other signals or satellites that are less vulnerable to that interference at that moment. Using hardware reconfigurability of FPGA receivers and characterizing the effect of narrowband interference on the GNSS signal quality lead us to a new RFI mitigation technique in which the highest quality and less vulnerable signal can be chosen at each moment. In the previous work [1], the post processing capability of a software GPS receiver, has been used to detect and characterize the CW interference. This is achieved by passing the GPS signal and the interference through the correlator. Then, using the conventional definition of C/No as the squared mean of the correlator output divided by its variance, the actual C/No for each satellite is calculated. In this work, first the 'Exclusion zone' for each satellite signal has been defined and then by using some experiments the effects of different parameters like signal power, jamming power and the environmental noise power on the Exclusion zone have been analyzed. By monitoring the Doppler frequency of each satellite and using the actual C/No of each satellite using the traditional definition of C/No and actual data from a software GPS receiver, the decision to reconfigure the receiver to other signal can be made.

• Journal of KIISE:Computer Systems and Theory
• /
• v.30 no.9
• /
• pp.512-522
• /
• 2003

For a time-multiplexed FPGA, a circuit is partitioned into several subcircuits, so that they temporally share the same physical FPGA device by hardware reconfiguration. In these architectures, all the hardware reconfiguration information called contexts are generated and downloaded into the chip, and then the pre-scheduled context switches occur properly and timely. Typically, the size of the chip required to implement the circuit depends on both the maximum number of the LUT blocks required to implement the function of each subcircuit and the maximum number of micro-registers to store results over context switches in the same time. Therefore, many partitioning or synthesis methods try to minimize these two factors. In this paper, we present a new estimation technique to find the lower bound on the number of micro-registers which can be obtained by any synthesis methods, respectively, without performing any actual synthesis and/or design space exploration. The lower bound estimation is very important in sense that it greatly helps to evaluate the results of the previous work and even the future work. If the estimated lower bound exactly matches the actual number in the actual design result, we can say that the result is guaranteed to be optimal. In contrast, if they do not match, the following two cases are expected: we might estimate a better (more exact) lower bound or we find a new synthesis result better than those of the previous work. Our experimental results show that there are some differences between the numbers of micro-registers and our estimated lower bounds. One reason for these differences seems that our estimation tries to estimate the result with the minimum micro-registers among all the possible candidates, regardless of usage of other resources such as LUTs, while the previous work takes into account both LUTs and micro-registers. In addition, it implies that our method may have some limitation on exact estimation due to the complexity of the problem itself in sense that it is much more complicated than LUT estimation and thus needs more improvement, and/or there may exist some other synthesis results better than those of the previous work.

• Journal of the Korean Institute of Intelligent Systems
• /
• v.9 no.6
• /
• pp.634-643
• /
• 1999

This paper concerns an implementation of f~rry logic controller (FLC') on a reconfigurahle FP