• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.8
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• pp.482-485
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• 2005

STSAT-2 is first satellite which is scheduled to launch by first Korea launcher. Ground station Baseband Controller(GBC) for operating STSAT-2 is now developing. GBC control data flow path between satellite operation computers and ground station antennas and count number of received data packets among demodulated audio signals from three antennas and also set data flow path to good-receiving antenna automatically In GBC two uplink FSK modulators(1.2kbps, 9.6kbps) and six downlink FSK demodulators(9.6kbps, 38.4kbps) are embedded. STSAT-2 GBC hardware is more simpler than STSAT-1 GBC by using FPGA in which all digital logic implemented. Now test and debugging of GBC hardware and Software(FPGA Code and CBC Manager Program) is well progressing in SaTReC, KAIST. This paper introduce GBC structure, functions and test results.

• Proceedings of the KIEE Conference
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• 2005.05a
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• pp.116-118
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• 2005

STSAT-2 is first satellite which is scheduled to launch by first Korea launcher. After launch Ground station Baseband Controller(GBC) for operating STSAT-2 is now developing. GBC control data flow path between satellite operation computers and ground station antennas. and GBC count number of received data packets among demodulated audio signals from three antennas and set data flow path to good-receiving antenna automatically. In GBC two uplink FSK modulators(1.2kbps, 9.6kbps) and six downlink FSK demodulators(9.6kbps, 38.4kbps) are embedded. STSAT-2 GBC hardware is more simpler than STSAT-1 GBC by using FPGA in which all digital logic implemented. Now test and debugging of GBC hardware and Software(FPGA Code and GBC Manager Program) is well progressing in SaTReC, KAIST. This paper introduce GBC structure, functions and test results.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.10
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• pp.130-137
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• 1990

The multipath multistage interconnection network is proposed which has the capability of dynamic rerouting. Construction of the network gets simpler, and the number of stages is reduced to $LOG_{2}$(N), so hardware complexity is reduced. This proposed algorithm makes it possible that destination adresses are used as routing tags, and it is easy to set up the path. Because this proposed network has a dynamic rerouting, backtracking is not necessary to set up another path when conflicts of switch faults are occurred. To estimate a performance, analytic methods are used and it is proved that probability of acceptance is improved in this Multipath MIN.

• Journal of Korean Society of Transportation
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• v.14 no.1
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• pp.51-67
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• 1996

The optimal path-finding problem becomes complicated when multiple variables are simultaneously considered such as physical route length, degree of congestion, traffic capacity of intersections, number of intersections and lanes, and existence of free ways. Therefore, many researchers in various fields (management science, computer science, applied mathematics, production planning, satellite launching) attempted to solve the problem by ignoring many variables for problem simplification, by developing intelligent algorithms, or by developing high-speed hardware. In this research, an integration of expert system technique and case-based reasoning in high level with a conventional algorithms in lower level was attempted to develop an optimal path-finding system. Early application of experienced driver's knowledge and case data accumulated in case base drastically reduces number of possible combinations of optimal paths by generating promising alternatives and by eliminating non-profitable alternatives. Then, employment of a conventional optimization algorithm provides faster search mechanisms than other methods such as bidirectional algorithm and $A^*$ algorithm. The conclusion obtained from repeated laboratory experiments with real traffic data in Seoul metropolitan area shows that the integrated approach to finding optimal paths with consideration of various real world constraints provides reasonable solution in a faster way than others.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.3A
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• pp.337-346
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• 2004

Punctured convolutional codes increase transmission efficiency without increasing hardware complexity. However, Viterbi decoder supporting punctured codes requires long decoding length and large survivor memory to achieve sifficiently low bit error rate (BER), when compared to the Viterbi decoder for a rate 1/2 convolutional code. This Paper presents novel architecture adopting a pipelined trace-forward unit reducing survivor memory requirements in the Viterbi decoder. The proposed survivor path architecture reduces the memory requirements by removing the initial decoding delay needed to perform trace-back operation and by accelerating the trace-forward process to identify the survivor path in the Viterbi decoder. Experimental results show that the area of survivor path unit has been reduced by 16％ compared to that of conventional hybrid survivor path unit.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.8C
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• pp.1113-1124
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• 2004

In this paper, we proposed a hardware(H/W) structure which can compress and recontruct the input image in real time operation and implemented it into a FPGA platform using VHDL(VHSIC Hardware Description Language). All the image processing element to process both compression and reconstruction in a FPGA were considered each of them was mapped into H/W with the efficient structure for FPGA. We used the DWT(discrete wavelet transform) which transforms the data from spatial domain to the frequency domain, because use considered the motion JPEG2000 as the application. The implemented H/W is separated to both the data path part and the control part. The data path part consisted of the image processing blocks and the data processing blocks. The image processing blocks consisted of the DWT Kernel fur the filtering by DWT, Quantizer/Huffman Encoder, Inverse Adder/Buffer for adding the low frequency coefficient to the high frequency one in the inverse DWT operation, and Huffman Decoder. Also there existed the interface blocks for communicating with the external application environments and the timing blocks for buffering between the internal blocks The global operations of the designed H/W are the image compression and the reconstruction, and it is operated by the unit of a field synchronized with the A/D converter. The implemented H/W used the 69%(16980) LAB(Logic Array Block) and 9%(28352) ESB(Embedded System Block) in the APEX20KC EP20K600CB652-7 FPGA chip of ALTERA, and stably operated in the 70MHz clock frequency. So we verified the real time operation of 60 fields/sec(30 frames/sec).

• Proceedings of the KIEE Conference
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• 1991.07a
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• pp.333-336
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• 1991

In this paper, Hopfield & Tank model-like artificial neural network structure is proposed, which can be used for the optimal path planning problems such as the unit commitment problems or the maintenance scheduling problems which have been solved by the dynamic programming method or the branch and bound method. To construct the structure of the neural network, an energy function is defined, of which the global minimum means the optimal path of the problem. To avoid falling into one of the local minima during the optimization process, the simulated annealing method is applied via making the slope of the sigmoid transfer functions steeper gradually while the process progresses. As a result, computer(IBM 386-AT 34MHz) simulations can finish the optimal unit commitment problem with 10 power units and 24 hour periods (1 hour factor) in 5 minites. Furthermore, if the full parallel neural network hardware is contructed, the optimization time will be reduced remarkably.

• The Journal of Korea Robotics Society
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• v.1 no.2
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• pp.117-124
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• 2006

In this paper, we develope the navigation system for patrol robots in indoor environment. The proposed system consists of PDA map modelling, a localization algorithm based on a global position sensor and an automatic charging station. For the practical use in security system, the PDA is used to build object map on the given indoor map. And the builded map is downloaded to the mobile robot and used in path planning. The global path planning is performed with a localization sensor and the downloaded map. As a main controller, we use PXA270 based hardware platform in which embedded linux 2.6 is developed. Data handling for various sensors and the localization algorithm are performed in the linux platform. Also, we implemented a local path planning algorithm for object avoidance with ultra sonar sensors. Finally, for the automatic charging, we use an infrared ray system and develop a docking algorithm. The navigation system is experimented with the two-wheeled mobile robot using North-Star localization system.

• Electronics and Telecommunications Trends
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• v.33 no.6
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• pp.58-68
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• 2018

A neuromorphic hardware that mimics biological perceptions and has a path toward human-level artificial intelligence (AI) was developed. In contrast with software-based AI using a conventional Von Neumann computer architecture, neuromorphic hardware-based AI has a power-efficient operation with simultaneous memorization and calculation, which is the operation method of the human brain. For an ideal neuromorphic device similar to the human brain, many technical huddles should be overcome; for example, new materials and structures for the synapses and neurons, an ultra-high density integration process, and neuromorphic modeling should be developed, and a better biological understanding of learning, memory, and cognition of the brain should be achieved. In this paper, studies attempting to overcome the limitations of next-generation neuromorphic hardware technologies are reviewed.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.41 no.4
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• pp.31-39
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• 2004

The ARM7 TDMI microprocessor employ a software routine iteration method in order to handle integer division operation, but this method has long execution time and many execution instruction. In this paper, we proposed ARM7 TDMI microprocessor with integer division instruction. To make this, we additionally defined UDIV instruction for unsigned integer division operation and SDIV instruction for signed integer division operation, and proposed ARM7 TDMI microprocessor data Path to apply division algorithm. Applied division algorithm is nonrestoring division algorithm and additive hardware is reduced using existent ARM data path. To verify the proposed method, we designed proposed method on RTL level using HDL, and conducted logic simulation. we estimated the number of execution cycles and the number of execution instructions as compared proposed method with a software routine iteration method, and compared with other published integer divider from the number of execution cycles and hardware size.