• Title/Summary/Keyword: Hardware Configuration

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Analysis of the Monopulse Radar Tracking Errors using Orthogonally Deployed Antenna Sets for Cross-eye Jamming (십자형으로 배치된 크로스아이 재머 안테나를 이용한 모노펄스 레이다 재밍 오차 분석)

  • Lim, Joong-Soo;Chae, Gyoo-Soo
    • Journal of Convergence for Information Technology
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    • v.10 no.6
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    • pp.14-18
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    • 2020
  • In this paper, when two sets of cross-eye jammer antennas are installed vertically to jam a monopulse radar, the jamming effects according to the jammer's phase difference, amplitude ratio, and radar angle of engagement are analyzed. The phase difference and amplitude ratio of the cross-eye jammer can be adjusted in the jammer, but since the angle of engagement is relatively determined by the radar, it is very important to respond to changes in the angle of engagement. The orthogonally deployed jammer antennas can be considered as a good way to increase the jamming effect while minimizing the hardware configuration, and the jamming effect is analyzed while changing the angle of inclination from 0° to 360°. This jammer greatly improves the jamming effects at the angles of incidence 45°~135° and 225°~315°, compared to a single jammer. And it is expected to be useful in the design of cross-eye jammers for military aircraft and ships.

A Novel Test Structure for Process Control Monitor for Un-Cooled Bolometer Area Array Detector Technology

  • Saxena, R.S.;Bhan, R.K.;Jalwania, C.R.;Lomash, S.K.
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.6 no.4
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    • pp.299-312
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    • 2006
  • This paper presents the results of a novel test structure for process control monitor for uncooled IR detector technology of microbolometer arrays. The proposed test structure is based on resistive network configuration. The theoretical model for resistance of this network has been developed using 'Compensation' and 'Superposition' network theorems. The theoretical results of proposed resistive network have been verified by wired hardware testing as well as using an actual 16x16 networked bolometer array. The proposed structure uses simple two-level metal process and is easy to integrate with standard CMOS process line. The proposed structure can imitate the performance of actual fabricated version of area array closely and it uses only 32 pins instead of 512 using conventional method for a $16{\times}16$ array. Further, it has been demonstrated that the defective or faulty elements can be identified vividly using extraction matrix, whose values are quite similar(within the error of 0.1%), which verifies the algorithm in small variation case(${\sim}1%$ variation). For example, an element, intentionally damaged electrically, has been shown to have the difference magnitude much higher than rest of the elements(1.45 a.u. as compared to ${\sim}$ 0.25 a.u. of others), confirming that it is defective. Further, for the devices having non-uniformity ${\leq}$ 10%, both the actual non-uniformity and faults are predicted well. Finally, using our analysis, we have been able to grade(pass or fail) 60 actual devices based on quantitative estimation of non-uniformity ranging from < 5% to > 20%. Additionally, we have been able to identify the number of bad elements ranging from 0 to > 15 in above devices.

The Development of HILS and Test Equipment for Millimeter-Wave (Ka-Band) Seeker's Test and Evaluation (밀리미터파 탐색기 시험 평가를 위한 HILS 및 시험 장비 개발)

  • Song, Sung-Chan;Na, Young-Jin;Yoon, Tae-Hwan
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.23 no.1
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    • pp.47-55
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    • 2012
  • This paper describes the developed HILS and test equipment in order to test the performances of MMW(Millimeter-Wave) seeker which can detect and track a high speed of short-range ballistic missile and aircraft. This system is used to 141 horn antenna array, array switching, and gain and phase control algorithm to simulate various kind of targets and trajectory of high speed and maneuver moving target. In addition, it simulates not only velocity and range for these targets but also clutter and jamming environments. System configuration and implementation and the measurement results of major subsystems such as target motion simulator, simulation signal generator, high speed data aquisition unit, and central control unit are presented. These systems could verify the detection and tracking performance of MMW seeker through dynamic real-time test based on simulation flight scenario.

Design and Implementation of Integrated Verification Facility for Satellite Flight Software (위성비행소프트웨어 통합검증환경의 설계 및 구축)

  • Shin, Hyun-Kyu;Lee, Jae-Seung;Choi, Jong-Wook;Cheon, Yee-Jin
    • Aerospace Engineering and Technology
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    • v.11 no.1
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    • pp.49-56
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    • 2012
  • The flight software monitors the status of the satellite and performs attitude control and its own mission. Due to the operating environments and its uniqueness, the high level of reliability is required for the flight software. To this end, a variety of activities to meet the given requirements and improve the safety and reliability are made during the development of flight software. A variety of development environments should be provided to support execution of flight software on hardware or satellite simulator and dynamic verification of flight software through command/telemetry interface. The satellite flight software team has been developing the IVF to be applied to various satellite projects more effectively and to improve the reliability of flight software. In this paper, the design and configuration method of IVF for the effective verification of flight software is introduced.

Symmetry structured SPN block cipher algorithm (대칭구조 SPN 블록 암호 알고리즘)

  • Kim, Gil-Ho;Park, Chang-Soo;Cho, Gyeong-Yeon
    • Journal of Korea Multimedia Society
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    • v.11 no.8
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    • pp.1093-1100
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    • 2008
  • Feistel and SPN are the two main structures in designing a block cipher algorithm. Unlike Feistel, an SPN has an asymmetric structure in encryption and decryption. In this paper we propose an SPN algorithm which has a symmetric structure in encryption and decryption. The whole operations in our SPN algorithm are composed of the even numbers of N rounds where the first half of them, 1 to N/2, applies function and the last half of them, (N+1)/2 to N, employs inverse function. Symmetry layer is executed to create a symmetry block in between function layer and inverse function layer. AES encryption and decryption algorithm, whose safety is already proved, are exploited for function and inverse function, respectively. In order to be secure enough against the byte or word unit-based attacks, 32bit rotation and simple logical operations are performed in symmetry layer. Due to the simplicity of the proposed encryption and decryption algorithm in hardware configuration, the proposed algorithm is believed to construct a safe and efficient cipher in Smart Card and RFID environments where electronic chips are built in.

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Performance Verification of a New Positioning Technology by Low-Resolution CDMA Pilot Strength Measurements (저해상도 CDMA Pilot 신호세기를 활용한 새로운 측위기법의 성능 검증)

  • Lee, Hyung Keun;Shim, Ju-Young;Kim, Hee-Sung
    • Journal of Advanced Navigation Technology
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    • v.11 no.2
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    • pp.154-162
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    • 2007
  • This paper verifies the performance of the wireless-signal map-matching (WSMM) method that is recently proposed to mitigate the effects of non-line-of-sight (NLOS) error in positioning under wireless terrestrial network environments. The WSMM method is the new positioning technology that estimates and compensate the NLOS errors by processing the bulks of anonymous measurements at unknown locations that are collected randomly and automatically. The WSMM method would be advantageous for various configurations of future ubiquitous sensor networks since it is based on the existing network configuration for communication and it requires no additional hardware in base stations and mobile handsets. It is shown that the application of the WSMM concept to the real CDMA pilot strength measurment message (PSMM) actually mitigates the NLOS error effects and improves overall positioning accuracy.

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A Study on MAC Core for 10Gbps Ethernet (10Gbps 이더넷용 MAC 코어에 대한 연구)

  • Sonh Seung-Il
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.9 no.3
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    • pp.547-554
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    • 2005
  • Ethernet has been given a greater attention recently due to tendency of unifying most of transmission technique to ethernet. This paper studied the design of MAC which contains high layer interface, transmit engine, flow control block, receive engine, reconciliation sublayer, configuration block, statistics block, and XGMll interface block. Performance evaluation was performed using C language for 10cbps ethernet Data Link to design the optimum hardware, then internal FIFO and initial parameters were evaluated. When offered load is $95\%$, the size of the internal FIFO is required 512-word. When offered load is $97\%$, the size of the internal FIFO is required 1024-word. Based on the result of performance evaluation, MAC was designed in VHDL Language and verified using simulator. MAC core that processes 64-bit data, operates at 168.549MHz and hence supports the maximum 10.78Gbps. The designed MAC core is applicable to an area that needs a high-speed data processing of 10Gbps or more.

Design and Verification of MAC Core for 10Gbps Ethernet Application (10Gbps 이더넷 응용을 위한 MAC 코어의 설계 및 검증)

  • Sonh Seung-Il
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.10 no.5
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    • pp.812-820
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    • 2006
  • Ethernet has been given a greater attention recently due to tendency of unifying most of transmission technique(not only LAN, but MAN and WAN) to ethernet. Performance evaluation was performed using C language for 10Gbps ethernet Data Link to design the optimum hardware, then internal FIFO size was evaluated. In this paper, MAC core for 10Gbps ethernet which contains high layer interface, transmit engine, flow control block, receive engine, reconciliation sublayer, configuration block, statistics block, and XGMII interface block was designed using VHDL language and Xilinx 6.2i tool and verified using Model_SIM 5.7G simulator. According to the specification of 10Gbps ethernet, MAC core with 64-bit data path should support 156.25MHz in order to support 10Gbps. The designed MAC core that process 64-bit data, operates at 168.549MHz and hence supports the maximum 10.78Gbps data processing. The designed MAC core is applicable to an area that needs a high-speed data processing of 10Gbps or more.

Measurements of Ultrasonic Velocity and Attenuation by Signal Processing Techniques in Time and Frequency Domains (시간 및 주파수 영역에서의 신호 처리 기술에 의한 초음파 속도와 감쇠의 측정)

  • Jang, Young-Su;Kim, Jin-Ho;Jeong, Hyun-Jo;Nam, Young-Hyun
    • Journal of the Korean Society for Nondestructive Testing
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    • v.19 no.2
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    • pp.118-128
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    • 1999
  • There are many ultrasonic measurement methods that are used in nondestructive testing applications. Some typical applications include material property determination, microstructural characterization. and flaw detection. Ultrasonic parameters such as velocity and attenuation are most commonly required in these applications. The accuracy and repeatability of testing results are dependent on both the hardware used to generate and receive the ultrasonic waves and on the analysis software for calculating these parameters. In this study, five analysis algorithms were implemented on a computer for measuring wave speed in a pulse echo. immersion testing configuration. In velocity measurements comparisons were made between the overlap. cross-correlation. Fourier transform. Hilbert transform, wavelet transform algorithms. Velocity measurement was applied to an isotropic steel sample using the five analysis algorithms. Frequency-dependent phase/group velocity and attenuation were also measured using the Fourier transform and wavelet transform algorithms on a composite laminate containing voids.

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Development of Fast Side-impact Sensing Algorithm (고속 측면 충돌 감지 알고리즘의 개발)

  • 박서욱;김현태
    • Transactions of the Korean Society of Automotive Engineers
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    • v.8 no.3
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    • pp.163-170
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    • 2000
  • Accident statistics shows that the portion of fatal occupant injuries due to side impacts is considerably high. The side impact usually leads to a severe intrusion of side structure into the passenger compartment. Furthermore, the safety zone for the side impact is relatively small compared to the front impact. Those kinds of physics for side impact frequently result in a fatal injury for the occupant. Therefore, NHTSA and EEVC are trying to intensify the regulation for the occupant protection against side impact. Both the regulation and recent market trends are asking for an installation of side airbag. There are several types of system configuration for side impact sensing. In this paper, we adopt the acceleration-based remote sensing method for the side airbag control system. We mainly focus on the development of hardware and crash discrimination algorithm of remote sensing unit. The crash discrimination algorithm needs fast decision of airbag firing especially for high-speed side impact such as FMVSS 214 and EEVC tests. It is also required to distinguish between low-speed fire and no-fire events. The algorithm should have a sufficient safety margin against any misuse situation such as hammer blow, door slam, etc. This paper introduces several firing criteria such as acceleration. velocity and energy criteria that use physical value proportional to crash severity. We have made a simulation program by using Matlab/Simulink to implement the proposed algorithm. We have conducted an algorithm calibration by using real crash data for 2,500cc vehicle. The crash performance obtained by the simulation was verified through a pulse injection method. It turned out that the results satisfied the system requirements well.

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