• Proceedings of the Korean Operations and Management Science Society Conference
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• 2006.05a
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• pp.1329-1333
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• 2006

This paper proposes a framework for product development including hardware and software components. The framework provides separation of the hardware dependent software, an integrated product development process, and integration of software components with product configurations and product structures. In order to separates the hardware dependent software, the framework considers product configuration modules and engineering changes of associated hardware and software components. The proposed product development process integrates development of the hardware dependent software into the existing product development process. In order to integrates the hardware dependent software with product configurations and product structures, the framework represents software components by existing product data models in Product Data Management (PDM). The framework is applied to development of a robot system including hardware and software components in order to show its effectiveness.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.7
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• pp.261-268
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• 1996

Hardware-software codesign becomes improtant to effectively sagisfy perfomrance goals, because designers can trade-off in the way hardware and software components work teogether to exhibit a specified behavior. In this paper, a hardware-software pratitioning algorithm is presetned, in which the system behavioral description containing a mixture of hardware and software components is partitioned into hardware part and software part. The partitioning algorithm tries to minimize the given cost function under constraints on hardware resources or latency. Recursive moving of operations between the hardware and software parts is used to find a near optimum partition and the list scheduling approach is used to estimate the hardware area and latency. Since memory may take substantial protion of the hardware part, memory cost is included in sthe hardware cost. Experimental resutls show that our algorithm is effective.

• ETRI Journal
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• v.28 no.4
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• pp.525-528
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• 2006

In this letter, we present a design of a single chip video decoder called advanced mobile video ASIC (A-MoVa) for mobile multimedia applications. This chip uses a mixed hardware/software architecture to improve both its performance and its flexibility. We designed the chip using a partition between the hardware and software blocks, and developed the architecture of an H.264 decoder based on the system-on-a-chip (SoC) platform. This chip contains 290,000 logic gates, 670,000 memory gates, and its size is $7.5\;mm{\times}7.5\;mm$ (using 0.25 micron 4-layers metal CMOS technology).

• ETRI Journal
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• v.31 no.6
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• pp.732-740
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• 2009

This paper describes the implementation of a digital audio effect system-on-a-chip (SoC), which integrates an embedded digital signal processor (DSP) core, audio codec intellectual property, a number of peripheral blocks, and various audio effect algorithms. The audio effect SoC is developed using a software and hardware co-design method. In the design of the SoC, the embedded DSP and some dedicated hardware blocks are developed as a hardware design, while the audio effect algorithms are realized using a software centric method. Most of the audio effect algorithms are implemented using a C code with primitive functions that run on the embedded DSP, while the equalization effect, which requires a large amount of computation, is implemented using a dedicated hardware block with high flexibility. For the optimized implementation of audio effects, we exploit the primitive functions of the embedded DSP compiler, which is a very efficient way to reduce the code size and computation. The audio effect SoC was fabricated using a 0.18 ${\mu}m$ CMOS process and evaluated successfully on a real-time test board.

• Journal of the Korean Society of Safety
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• v.34 no.1
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• pp.21-26
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• 2019

This paper is purposed to develop hardware for controlling abnormal temperature that can occur environment and component itself in PCS. In order to be purpose, the hardware which is four part(sensing, PLC, monitoring and output) keep detecting temperature for critical components of PCS and can control the abnormal temperature. Apply to the hardware, it is selected to PV power generation facilities of 20 kW in Cheong-ju city and measured the data for one year in 2017. Through the temperature data, it is found critical components of four(discharge resistance, DC capacitor, IGBT, DSP board) and entered the setting value for operating the fan. The setting values for operating the fan are up to $130^{\circ}C$ in discharge resistance, $60^{\circ}C$ in DC capacitor, $55^{\circ}C$ in IGBT and DSP board. The hardware is installed at the same PCS(20 kW in Cheong-ju city) in 2018 and the power generation output is analyzed for the five days with the highest atmospheric temperature(Clear day) in July and August in 2017 and 2018 years. Therefore, the power generation output of the PV system with hardware increased up to 4 kWh.

• Smart Media Journal
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• v.11 no.11
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• pp.32-39
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• 2022

As IoT applications that provide AI services increase, various hardware and software that support autonomous learning and inference are being developed. However, as the characteristics and constraints of each hardware increase difficulties in developing IoT applications, the development of an integrated platform is required. In this paper, we propose a tool for automatically generating components based on artificial neural networks and spiking neural networks as well as IoT technologies to be compatible with open platforms. The proposed component automatic generation tool supports the creation of components considering the characteristics of various hardware devices through the virtual component layer of IoT and AI and enables automatic application to open platforms.

• Journal of Multimedia Information System
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• v.6 no.1
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• pp.7-14
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• 2019

This work presents a virtual prototyping design approach for an area-based image stitching hardware. The virtual hardware obtained from virtual prototyping is equivalent to the conceptual algorithm, yet the conceptual blocks are linked to the actual circuit components including the memory, logic gates, and arithmetic units. Through the proposed method, the overall structure, size, and computation speed of the actual hardware can be estimated in the early design stage. As a result, the optimized virtual hardware facilitates the hardware implementation by eliminating trail design and redundant simulation steps to optimize the hardware performance. In order to verify the feasibility of the proposed method, the virtual hardware of an image stitching platform has been realized, where it required 10,522,368 clock cycles to stitch two $1280{\times}1024$ sized images. Furthermore, with a clock frequency of 250MHz, the estimated computation time of the proposed virtual hardware is 0.877sec, which is 10x faster than the software-based image stitch platform using MATLAB.

• Journal of KIISE:Software and Applications
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• v.36 no.8
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• pp.607-615
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• 2009

There has recently been a trend that IT industry is united with traditional industries such as military, aviation, automobile, and medical industry. Therefore, embedded software which controls hardware of the system should guarantee the high reliability, availability, and maintainability. To guarantee these properties, there are many attempts to develop the embedded software based on COTS (Commercial Off The Shelf) hardware components. However, it can cause additional faults due to software/hardware interactions beside general software faults in this methodology. We called the faults, Linkage Fault. These faults have high severity that makes overall system shutdown although their occurrence frequency is extremely low. In this paper, we propose a new software reliability model which considers those linkage faults in embedded software development with COTS hardware components. We use the Bayesian Analysis and Markov Chain Monte-Cairo method to validate the model. In addition, we analyze real linkage fault data to support the results of the theoretical model.

• Proceedings of the Korean Reliability Society Conference
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• 2011.06a
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• pp.271-279
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• 2011

Automotive safety integrity level of hardware components can be achieved by satisfying quantitative and qualitative requirements. Based on ASIL, quantitative requirements are composed of hardware architectural metrics and evaluation of safety goal violations due to random hardware failures in ISO 26262. In this paper, the types of hardware failures will be defined and classified. Based on various metrics related with hardware failures, design essentials to achieve hardware safety integrity will be studied specifically. Issues associated with hardware development and assessment process are presented briefly.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.1
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• pp.20-26
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• 2021

Recent systems contain hardware and software components together for faster execution speed and less power consumption. In conventional hardware and software co-design, the ratio of software and hardware was divided by the designer's empirical knowledge. To find optimal results, designers iteratively reconfigure accelerators and applications and simulate it. Simulating iteratively while making design change is time-consuming. In this paper, we propose a hardware and software co-design platform for energy-efficient FPGA accelerator design. The proposed platform makes it easy for designers to find an appropriate hardware ratio by automatically generating application program code and hardware code by parameterizing the components of the accelerator. The co-design platform based on the Vitis unified software platform runs on a server with Xilinx Alveo U200 FPGA card. As a result of optimizing the multiplication accelerator for two matrices with 1000 rows, execution time was reduced by 90.7% and power consumption was reduced by 56.3%.