• ETRI Journal
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• v.28 no.1
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• pp.31-44
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• 2006

In a packet switching network, congestion is unavoidable and affects the quality of real-time traffic with such problems as delay and packet loss. Packet fair queuing (PFQ) algorithms are well-known solutions for quality-of-service (QoS) guarantee by packet scheduling. Our approach is different from previous algorithms in that it uses hardware time achieved by sampling a counter triggered by a periodic clock signal. This clock signal can be provided to all the modules of a routing system to get synchronization. In this architecture, a variant of the PFQ algorithm, called digitized delay queuing (DDQ), can be distributed on many line interface modules. We derive the delay bounds in a single processor system and in a distributed architecture. The definition of traffic contribution improves the simplicity of the mathematical models. The effect of different time between modules in a distributed architecture is the key idea for understanding the delay behavior of a routing system. The number of bins required for the DDQ algorithm is also derived to make the system configuration clear. The analytical models developed in this paper form the basis of improvement and application to a combined input and output queuing (CIOQ) router architecture for a higher speed QoS network.

• Journal of IKEEE
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• v.23 no.3
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• pp.1092-1095
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• 2019

In this paper, we propose the development of an embedded board for construction of smart factory. The proposed embedded board for construction of smart factory consists of main module, ADC module, I/O module. Main module is a main calculating device which includes communication pard that allows interface with external device with using industrial protocol and is ported operating system makes board operating into. ADC module takes part in transferring digital signal has converted from electrical signal to the main module from the external sensor which is installed on the field. I/O module is an input and output module which transfers to the main module about a status, alarm, command signal of field device and it has a function that blocks external noises from field device with isolation circuit into it. In order to evaluate the performance of the proposed embedded board for construction of smart factory, it has been tested by an authorized testing institute. As a result, quantity of interacting protocol was 5, speed of hardware clock synchronization was under 10us and operating time of battery without source power was over 8 hours. It produced the same result as the world's highest level.

• Journal of Broadcast Engineering
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• v.23 no.2
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• pp.197-205
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• 2018

Panoramic image is one of the technologies that are commonly used today. However, technical difficulties still exist in panoramic video production. Without a special camera such as a 360-degree camera, making panoramic video becomes more difficult. In order to make a panoramic video, it is necessary to synchronize the timeline of multiple videos shot at multiple locations. However, the timeline synchronization method using the internal clock of the camera may cause an error due to the difference of the internal hardware. In order to solve this problem, timeline synchronization between multiple videos using visual information or auditory information has been studied. However, there is a problem in accuracy and processing time when using video information, and there is a problem in that, when using audio information, there is no synchronization when there is sensitivity to noise or there is no melody. Therefore, in this paper, we propose a timeline synchronization method between multiple video using audio waveform. It shows higher synchronization accuracy and temporal efficiency than the video information based time synchronization method.

• Journal of Institute of Control, Robotics and Systems
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• v.22 no.8
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• pp.671-677
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• 2016

A Controller Area Network (CAN) is a serial communication protocol that is highly reliable and efficient in many aspects, such as wiring cost and space, system flexibility, and network maintenance. Therefore, it is chosen for the communication protocol between a single chip controller based on Field Programmable Gate Array (FPGA) and peripheral devices. In this paper, the design and implementation of CAN IP, which is written in VHSIC Hardware Description Language (VHDL), is presented. The implemented CAN IP is based on the CAN 2.0A specification. The CAN IP consists of three processes: clock generator, bit timing, and bit streaming. The clock generator process generates a time quantum clock. The bit timing process does synchronization, receives bits from the Rx port, and transmits bits to the Tx port. The bit streaming process generates a bit stream, which is made from a message received from a micro controller subsystem, receives a bit stream from the bit timing process, and handles errors depending on the state of the CAN node and CAN message fields. The implemented CAN IP is synthesized and downloaded into SmartFusion FPGA. Simulations using ModelSim and chip test results show that the implemented CAN IP conforms to the CAN 2.0A specification.

• The Transactions of the Korea Information Processing Society
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• v.4 no.2
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• pp.363-376
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• 1997

In this paper, we present a hardware architecture and a sofrware architecture for cimputer based teleconferencing systems.And also we analyse stream adtivation mechanisms for them form the viewpoint of delay. MuX that is a multimedia I/O server provides various processing elements for data I/O, synchronization, interleaving and mixing.We describe methods to build teleconferencing systems with the elements and compares the technique using master click with the techniquie using self clock.In the plase of dta input.the technique using self click is berrer than the technique using master clock.When we generate interleved stream from audio and video stream and activate channel objects by periodic audio stream as activation clock, dealy from imput audio stream to imterleved stream is reduced but delay for video stream is not reduced as much as in the case of audio stream.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.57 no.2
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• pp.109-114
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• 2008

In this paper, a dynamic learning controller for robot manipulator is implemented using real-time operating system with capabilities of multitasking, intertask communication and synchronization, event-driven, priority-driven scheduling, real-time clock control, etc. The controller hardware system with VME bus and related devices is developed and applied to implement a dynamic learning control scheme for robot manipulator. Real-time performance of the proposed dynamic learning controller is tested and evaluated for tracking of the desired trajectory and compared with the conventional servo controller.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.48 no.6
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• pp.18-26
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• 2011

Debates concerning the competitive edge of leading 3DTV technology of the shutter glasses (SG) 3D and the film-type patterned retarder (FPR) are flaring up. Although SG technology enables Full-HD 3D vision, it requires complex systems including the sync transmitter (emitter), the sync processor chip, and the LCD lens in the active shutter glasses. In addition, the transferred sync-signal is easily affected by the external noise and a 3DTV viewer may feel flicker-effect caused by cross-talk of the left and right image. The operating current of the sync processor in the 3DTV active shutter glasses is gradually increasing to compensate the sync reconstruction error. The proposed chip is a low-power hardware sync processor based discrete-event SoC(system on a chip) designed specifically for the 3DTV active shutter glasses. This processor implements the newly designed power-saving techniques targeted for low-power operation in a noisy environment between 3DTV and the active shutter glasses. This design includes a hardware pre-processor based on a universal edge tracer and provides a perfect sync reconstruction based on a floating-point timer to advance the prior commercial 3DTV shutter glasses in terms of their power consumption. These two techniques enable an accurate sync reconstruction in the slow clock frequency of the synchronization timer and reduce the power consumption to less than about a maximum of 20% compared with other major commercial processors. This article describes the system's architecture and the details of the proposed techniques, also identifying the key concepts and functions.

• The KIPS Transactions:PartC
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• v.15C no.1
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• pp.31-36
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• 2008

The clock frequency difference of sensor nodes is one of main parameters in TOF estimation and affect to degrade ranging algorithms to estimate positions of mobile nodes in wireless sensor networks. The specification of IEEE802.15.4a describes asynchronous TWR and SDS-TWR insensitive to frequency difference without any additional network synchronization. But the TWR and SDS-TWR can not eliminate sufficiently the effect of frequency difference of node pair, packet processing delay and its difference. Especially use of low cost oscillator with wide range offset, sensor node with different hardware and software can make the positioning errors worse. We propose an estimation method of frequency differences, and apply the measured frequency differences to TWR and SDS-TWR. We evaluate the performance of the proposed algorithm with simulation, and make certain that the proposed method enhances the performance of existing algorithms with positioning errors less than 25 cm.