• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.5
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• pp.1-10
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• 1998

In this paper, a new hardware-software patitioning algorithm is presented, in which the system behavioral description containing a mixture of hardware and softwae components is partitioned into the hardware part and the software part. In this research, new techniques to optimally partition a mixed system under certain specified constaints such as performance, area, and delay, have been developed. During the partitioning process, the overhead due to the communication between the hardware and software parts are considered. New featues have been added to adjust the hierarchical level of partitioning. Power consumption, memory cost, and the effect of pipelining can also be considered during partitioning. Another new feature is the ability to partition a DSP system under throughput constraints. This feature is important for real time processing. The developed partitioning system can also be used to evaluate various design alternatives and architectures.

• Journal of KIISE
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• v.42 no.2
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• pp.177-182
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• 2015

The era of multi-core processors has begun since the limit of the clock speed has been reached. These days, multi-core technology is used not only in desktops, servers, and table PCs, but also in smartphones. In this architecture, there is always interference between processes, because of the sharing of system resources. To address this problem, cache partitioning is used, which can be roughly divided into two types: software and hardware cache partitioning. When it comes to dynamic cache partitioning, hardware cache partitioning is superior to software cache partitioning, because it needs no page copy. In this paper, we compare the effectiveness of hardware and software cache partitioning on the AMD Opteron 6282 SE, which is the only commodity processor providing hardware cache partitioning, to see whether this technique can be effectively deployed in dynamic environments.

• The KIPS Transactions:PartA
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• v.11A no.5
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• pp.303-312
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• 2004

In this paper, we propose a methodology solving the problem of the hardware-software partitioning in reconfigurable systems using a Y-chart design space exploration and implement a simulator according to the methodology. The methodology generates a mapping set between tasks and hardware elements using the hardware element model and the application model. We evaluate the throughput by simulating cases in each mapping set. With the throughput evaluation result, we can select the mapping case with the highest throughput. We also propose an heuristic improving the simulation time by reducing the mapping set on the basis of the relationship between workload and parallelism. Simulation results show that we can reduce the size of mapping set which poses difficulties on hardware-software partitioning by up to 80%.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.7
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• pp.261-268
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• 1996

Hardware-software codesign becomes improtant to effectively sagisfy perfomrance goals, because designers can trade-off in the way hardware and software components work teogether to exhibit a specified behavior. In this paper, a hardware-software pratitioning algorithm is presetned, in which the system behavioral description containing a mixture of hardware and software components is partitioned into hardware part and software part. The partitioning algorithm tries to minimize the given cost function under constraints on hardware resources or latency. Recursive moving of operations between the hardware and software parts is used to find a near optimum partition and the list scheduling approach is used to estimate the hardware area and latency. Since memory may take substantial protion of the hardware part, memory cost is included in sthe hardware cost. Experimental resutls show that our algorithm is effective.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.9
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• pp.66-77
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• 2000

This paper presents a fast partitioning heuristic for hardware/software codesign called Best Imaginary Level-Iterative(BILI) partitioning which iteratively applies BIL heterogeneous multiprocessor scheduling heuristic to minimize the cost within the given time constraint. The proposed algorithm solves the partitioning problem with the implementation bin selection problem as well as architectures with multiple software modules. It costs about 15% less than the GCLP and at most about 5% more than the optimal solution obtained by the Integer Linear Programming(ILP) algorithm.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.65-68
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• 2002

The verification of software part and HW/SW interface suffer from the absence of the hardware platform at the end of partitioning and coding phase in design cycle. In this paper we present the design of easy verification for hardware design. Hardware and software engineer can verify their software program and hardware design for a chip that is emulated in proposed verification environment. Besides, designer can easily design the DEMO system.

• The KIPS Transactions:PartD
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• v.15D no.1
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• pp.87-98
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• 2008

In company with the demand of powerful processing units for embedded systems, the method to develop embedded software is also required to support the demand in new approach. In order to improve the resource utilization and system performance, software modeling techniques have to consider the features of hardware architecture. This paper proposes a partitioning technique of UML-based software models, which focus the generation of the allocatable software components into multiprocessor architecture. Our partitioning technique, at first, transforms UML models to CBCFGs(Constraint-Based Control Flow Graphs), and then slices the CBCFGs with consideration of parallelism and data dependency. We believe that our proposition gives practical applicability in the areas of platform specific modeling and performance estimation in model-driven embedded software development.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.153-156
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• 2000

This paper presents a SOC design methodology using the newly-emerging SystemC. The suggested methodology firstly uses SystemC to define blocks from the previously-developed system level algorithm with internal behavior and interface being separated and validate such a described blocks' functionality when integrated. Next, the partitioning between software and hardware is considered. With software, the interface to hardware is described cycle-accurate and the other internal behavior in conventional ways. With hardware, I/O transactions are refined gradually in several abstraction levels and internal behavior described on a function basis. Once hardware and software have been completed functionally, system performance analysis is performed on the built model with assumed performance factors and influences such decisions regressively as on optimum algorithm selection, partitioning and etc. The analysis then gives constraint information when hardware description undergoes scheduling and fixed-point trans- formation with the help of automatic translation tools or manually. The methodology enables C/C++ program developers and VHDL/Verilog users to migrate quickly to a co-design & co-verification environment and is suitable for SoC development at a low cost.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.553-556
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• 2004

In this paper, we present a new efficient multi-level hardware/software partitioning algorithm for system-on-a-chip design. Originally the multi-level partitioning algorithm are proposed to enhance the performance of previous iterative improvement partitioning algorithm for large scale circuits. But when designing very complex and heterogeneous SoCs, the HW/SW partitioning decision needs to be made prior to refining the system description. In this paper, we present a new method, based on multi-level algorithm, which can cover SoC design. The different variants of algorithm are evaluated by a randomly generated test graph. The experimental results on test graphs show improvement average $9.85\%$ and $8.51\%$ in total communication costs over FM and CLIP respectively.

• Proceedings of the Korean Information Science Society Conference
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• 2002.04a
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• pp.22-24
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• 2002

본 논문에서는 백트랙킹 알고리즘을 이용한 하드웨어/소프트웨어 분할 방법을 제안한다. 최적의 해를 찾을 때에 효율적인 가지치기 함수를 정의하여 불필요한 탐색 단계를 제거하므로써 계산 시간이 단축될 수 있도록 하였다. 또한 제약조건에 따라 트리의 검색 순서에 변화를 주어 효율적인 검색이 되도록 하였다. 제안된 알고리즘의 성능평가를 위해 시뮬레이티드 어닐링 방법의 결과와 비교 분석하였다.