• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2018.06a
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• pp.217-220
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• 2018

본 논문에서는 딥러닝을 활용한 비디오 보간법(video interpolation)에 대한 최근 모델들을 HD 급 비디오로 학습시키는 방법과 평가 성능을 비교 분석하는 것을 목표로 한다. 기존의 딥러닝을 활용한 비디오 보간법에 대해 제안된 모델들은 낮은 해상도의 비디오로 실험을 진행하였다. 반면 본 연구에서는 한정된 메모리를 가지고도 높은 해상도의 비디오를 학습시키기 위해서 패치 단위 데이터 셋을 구성하여 학습을 진행하였다. 평가 성능을 보이기 위해서 학습 데이터와 마찬가지로 패치 단위 평가와 전체 프레임 단위 평가 성능의 결과를 비교한다.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2018.06a
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• pp.156-157
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• 2018

최근 가정용 TV 를 포함한 비디오 디스플레이 기기는 HD(High Definition)에서 UHD(Ultra High Definition)로 급속하게 전환되고 있다. DTV 방송의 경우 한국은 HDR(High Dynamic Range)이 제외된 UHDTV 지상파 방송을 시작하였고 북미 MVPD(Multiple Video Program Distributor) 사업자들은 HDR 서비스를 먼저 도입하기 시작하였다. 기존 full HD 보다 4 배 이상의 해상도를 지원하는 UHD 는 HDR 과 WCG(Wide Color Gamuit)를 제외하고 논할 수 없다. 본 고에서는 해외의 디스플레이 인증 기관에서 적용하고 있는 UHD 디스플레이 디바이스에 대한 화질 평가 기술에 대하여 소개한다.

• Broadcasting and Media Magazine
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• v.4 no.4
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• pp.46-51
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• 1999

The introduction of broadcast digital television (DTV) was, at one time, seen as an opportunity to rationalise video formats. The reality is quite different with a rapid divergence as the united States' ATSC offers 18 formats to cover both standard definition (SD) and high definition (HD), and yet more are supported by Europe's DVB. At the same time multi-media is expanding both as an area for source material and for finished work. Post production needs to move away from single-format facilities as requirements for multi-format operation is already increasing. A 'format-independent' solution is described which allows efficient operation with any mix of input formats and able to output any format with high quality. Attention is given to retaining the speed, accuracy and immediacy which is a feature of today's professional facilities -even while handling the greater demands of HD. Another route, using 24 frames-per-second is also examined.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.569-572
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• 2005

This paper proposed the design and implementation of a DSP platform for the various multimedia streaming. The DSP platform synchronizes with host PC to configure DSP and to transmit multimedia streaming through PCI. The suggested DSP platform decodes high-capacity video/audio data using the suggested high-speed FIFO, CPLD and memory interface. The buffer control techniques is proposed in other to avoid the under/over-run of the audio/video data during the audio/video decoding. For the DSP platform test, host PC transmits program stream(PS) that consists of the MPEG-2 video MP@ML and 5.1ch AC3 audio data (Coyote.mov file, half hour running time) to DSP platform. The DSP platform plays continuously back the high sound-quality audio and high-definition video at once.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.4
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• pp.2363-2369
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• 2014

The DVR system supports multiple cameras and should be able to receive images at 30 frames per channel in real time. Thus, The system is using Full-HD-grade Multiplexer and Hardware compression codec. In this paper, Describing the design and implementation for the 4-channel Full-HD-grade PC-based DVR using FPGA and GPU inside CPU without Multiplexer and Hardware codec. The existing DVR system for Full-HD-grade has drawbacks to acquire images of about only 20 frames per channel in real time. The system to acquire images of multiple channel in real time was designed using FPGA. The software for the system was implemented using Intel Media SDK. At the result of performance evaluation, It was satisfied all for the required conditions. The practicality of the system was confirmed as implementation the system without using hardware compression.

• Journal of Satellite, Information and Communications
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• v.9 no.1
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• pp.13-16
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• 2014

In applying LCD to TV application, one of the most significant factors to be improved is image sticking on the moving picture. LCD is different from CRT in the sense that it's continuous passive device, which holds images in entire frame period, while impulse type device generate image in very short time. To reduce image sticking problem related to hold type display mode, we made an experiment to drive TN-LCD like CRT. We made articulate images by fast refreshing images, and we realized the ratio of refresh time by counting between on time and off time for video signal input during 1 frame (16.7ms). Conventional driving signal cannot follow fast on-off speed, so we evaluated new signal generator using SDI (Serial Data Interface) mode signal generator. We realized articulate image generation similar to CRT by high fast full HD (High Definition) signals and TN-LCD overdriving. As a result, reduced image sticking phenomenon was validated by naked eye and response time measurement.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.12
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• pp.167-173
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• 2015

This paper presents a study on the Full-HD HEVC(High Efficiency Video Coding) encoder IP(Intellectual Property) design. The designed IP is for HEVC main profile 4.1, and performs encoding with a speed of 60 fps of full high definition. Before hardware and software design, overall reference model was developed with C language, and we proposed a parallel processing architecture for low-power consumption. And also we coded firmware and driver programs relating IP. The platform for verification of developed IP was developed, and we verified function and performance for various pictures under several encoding conditions by implementing designed IP to FPGA board. Compared to HM-13.0, about 35% decrease in bit-rate under same PSNR was achieved, and about 25% decrease in power consumption under low-power mode was performed.

• Journal of Digital Convergence
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• v.10 no.6
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• pp.241-246
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• 2012

In this paper, we apply the next generation Internet Broadcasting Move Picture solution, FlashVideo has been designed and implemented. Currently being broadcast in the field to compress HD video in real time, as well as live Internet VOD services are available through the online system, the Internet LIVE broadcast and VOD service easy to operate and UCC services that support the solution. VOD video cameras and in real time using H264 CORECODEC to compress MPEC4, WMV, and real-time video streaming on the Internet, and phone system that supports the first, real-time recording of camera images featured nation's first real-time encoder system (Real time encoder system) is, Web and smart environment suitable for supporting the latest CORECODEC technology and software products. Second, the video can be played in MP4 player and customize your chat, and customizing is a possible two-way Internet Broadcasting System. Third, CMS (Contents Management System) feature video contents and course management contents in real time via the Android phone and iPhone streaming service is available.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.11
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• pp.71-76
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• 2008

H.264(or MPEG-4/AVC pt.10) is a high performance video coding standard, and is widely used. Variable length code (VLC) of the H.264 standard compresses data using the statistical distribution of values. A decoder parses the compressed bit stream and searches decoded values in lookup tables, and the decoding process is not easy to implement by hardware. We propose an architecture of variable length decoder(VLD) for the H.264 baseline profile(BP) L4. The CAVLD decodes syntax elements using the combination of arithmetic units and lookup tables for the optimized hardware architecture. A barral shifter and a first 1's detector parse NAL bit stream, and are shared by Exp-Golomb decoder and CAVLD. A FIFO memory between CAVLD and the reorder unit and a buffer at the output of the reorder unit eliminate the bottleneck of data stream. The proposed VLD is designed using Verilog-HDL and is implemented using an FPGA. The synthesis result using a 0.18um standard CMOS technology shows that the gate count is 22,604 and the decoder can process HD($1920{\times}1080$) video at 120MHz.

• Journal of Broadcast Engineering
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• v.20 no.4
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• pp.497-508
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• 2015

Current communication networks consist of channels with various throughputs, protocols, and packet loss rates. Moreover, there are also diverse user multimedia consumption devices having different capabilities and screen sizes. Thus, a practical necessity of scalability on video coding have been gradually increasing. Recently, The Scalable High Efficiency Video Coding(SHVC) standard is developed by Joint Collaborative Team on Video Coding(JCT-VC) organized in cooperation with MPEG of ISO/IEC and VCEG of ITU-T. This paper introduces coding tools of SHVC including adopted and unadopted tools discussed in the process of the SHVC standardization. Furthermore, the individual tool and combined tool set are evaluated in terms of coding efficiency relative to a single layer coding structure. This analysis would be useful for developing a fast SHVC encoder as well as researching on a new scalable coding tool.