• Title/Summary/Keyword: HC(Hot Carrier Stress)

Search Result 2, Processing Time 0.02 seconds

Study of relation between gate overlap length and device reliability in amorphous InGaZnO thin film transistors (비정질 InGaZnO 박막트랜지스터에서 Gate overlap 길이와 소자신뢰도 관계 연구)

  • Moon, Young-Seon;Kim, Gun-Young;Jeong, Jin-Yong;Kim, Dae-Hyun;Park, Jong-Tae
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
    • /
    • 2014.10a
    • /
    • pp.769-772
    • /
    • 2014
  • The device reliability in amorphous InGaZnO under NBS(Negative Bias Stress) and hot carrier stress with different gate overlap has been characterized. Amorphous InGaZnO thin film transistor has been measured. and is channel $width=104{\mu}m$, $length=10{\mu}m$ with gate overlap $length=0,1,2,3{\mu}m$. The device reliability has been analyzed by I-V characteristics. From the experiment results, threshold voltage variation has been increased with increasing of the gate overlap length after hot carrier stress. Also, threshold voltage variation has been decreased and Hump Effect has been observed later with increasing of the gate overlap length after NBS.

  • PDF

Submicron CMOSFET에서 기판 방향에 대한 소자 성능 의존성 분석

  • Park, Ye-Ji;Han, In-Sik;Park, Sang-Uk;Gwon, Hyeok-Min;Bok, Jeong-Deuk;Park, Byeong-Seok;Lee, Hui-Deok
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
    • /
    • 2009.11a
    • /
    • pp.7-7
    • /
    • 2009
  • In this paper, we investigated the dependence of HCI (Hot Carrier Immunity) degradation and device performance on channel orientation in sub-micron PMOSFET. Although device performance ($I_{D.sat}$ vs. $I_{Off}$) was improved as the transistor angle increased HC immunity was degraded. Therefore, consideration of reliability characteristics as well as dc device performance is highly necessary in channel stress engineering of next generation CMOSFETs.

  • PDF