• Proceedings of the IEEK Conference
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• 2003.11a
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• pp.83-86
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• 2003

In this paper, we propose a new hardware architecture for integer transform, quantizer operation of a new video coding standard H.264/JVT. We describe the algorithm to derive hardware architecture emphasizing the importance of area for low cost and low power consumption. The proposed architecture has been verified by PCI-interfaced emulation board using APEX-II Altera FPGA and also by ASIC synthesis using Samsung 0.18 ${\mu}{\textrm}{m}$ CMOS cell library. The ASIC synthesis result shows that the proposed hardware can operate at 100 MHz, processing more than 1, 300 QCIF video frames per second. The hardware is going to be used as a core module when implementing a complete H.264 video encoder/decoder ASIC for real-time multimedia application.

• Proceedings of the IEEK Conference
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• 2003.07e
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• pp.1928-1931
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• 2003

본 논문은 가장 최근의 동영상 국제표준인 H.264 비디오 코덱을 사용하여 QCIF 영상을 초당 10 프레임 정도의 속도로 실시간 부호화하는 것을 목적으로, 부호화 시 필요한 연산의 약 80％-90％를 차지하는 움직임 추정을 고속으로 처리할 수 있는 알고리즘을 개발하는 것을 내용으로 하고 있다. 제안하는 고속 움직임 추정 알고리즘은 MPEG겨 등의 고속 움직임 추정에 사용되었던 기존의 알고리즘을 다중 프레임 레퍼런스 등 새로운 특징을 갖는 H.264 코덱에 적합한 형태로 개선하고, 움직임 추정의 정밀도가 1/4 화소 단위로 향상됨으로써 늘어난 부화소단위 움직임 추정의 상대적 부담을 함께 고려하면서, 모드 선택과정과 효과적으로 결합함으로써 보다 향상된 성능을 나타내고 있다. 모의실험 결과, 기존의 공식 JVT-AVC 레퍼런스 소프트웨어인 JM (Joint Model) 에 구현되어 있는 고속 움직임 추정 알고리즘에 비해서 최대 80％, 평균적으로 60％의 속도개선 효과가 있음이 입증되어, 최근 JM 의 새로운 고속 움직임 추정 알고리즘으로 채택된 JVT-F0l7 알고리즘에 본 논문에서 제안하는 레퍼런스 프레임 탐색 제한 알고리즘을 결합시킴으로써 추가적으로 약 45％의 속도 개선을 얻을 수 있음을 확인하였다.

• Journal of The Institute of Information and Telecommunication Facilities Engineering
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• v.10 no.2
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• pp.53-61
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• 2011

This research presents an adaptive fast motion estimation (ME) computation on the stage of uneven multi-hexagon grid search (UMHGS) algorithm included in an unsymmetrical-cross multi-hexagon-grid search (UMHexagonS) in H.264 standard. The proposed adaptive method is based on statistical analysis and previously obtained motion vectors to reduce the computational complexity of ME. For this purpose, the algorithm is decomposed into three processes: skipping, terminating, and reducing search areas. Skipping and terminating are determined by the statistical analysis of the collected minimum SAD (sum of absolute difference) and the search area is constrained by the slope of previously obtained motion vectors. Simulation results show that 13%-23% of ME time can be reduced compared with UMHexagonS, while still maintaining a reasonable PSNR (peak signal-to-noise ratio) and average bitrates.

• ETRI Journal
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• v.28 no.5
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• pp.574-582
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• 2006

In this paper, a new error concealment algorithm is proposed for the H.264 standard. The algorithm consists of two processes. The first process uses a fuzzy logic method to select the size type of lost blocks. The motion vector of a lost block is calculated from the current frame, if the motion vectors of the neighboring blocks surrounding the lost block are discontinuous. Otherwise, the size type of the lost block can be determined from the preceding frame. The second process is an error concealment algorithm via a proposed adapted multiple-reference-frames selection for finding the lost motion vector. The adapted multiple-reference-frames selection is based on the motion estimation analysis of H.264 coding so that the number of searched frames can be reduced. Therefore the most accurate mode of the lost block can be determined with much less computation time in the selection of the lost motion vector. Experimental results show that the proposed algorithm achieves from 0.5 to 4.52 dB improvement when compared to the method in VM 9.0.

• Annual Conference of KIPS
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• 2007.05a
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• pp.341-344
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• 2007

In this paper, a new temporal error concealment method for the new coding standard H.264/AVC is presented, which uses the high correlation between the motion vectors of neighboring blocks. By using the motion vector of neighboring MB of the lost MB, the MV of the lost MB are recovered. It is shown that under FMO coding method of H.264/AVC, the proposed method increases PSNR gain up to 2.85dB compared to build-in algorithm in the H.264/AVC test model and 2.59dB compared to Lagrange interpolation.

• The KIPS Transactions:PartD
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• v.14D no.7
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• pp.801-808
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• 2007

Video coding standards such as MPEG-2, MPEG-4, H.263, and H.264 transmit a compressed video data using wired/wireless communication line with limited bandwidth. Because highly compressed bit-streams is likely to fragile to error from channel noise, video is damaged by error. There have been many research works on error concealment techniques, which recover transmission errors at decoder side [1, 2]. We designed an error concealment technique for lost motion vectors of H.264 video coding. In this paper, we propose a Kalman filter based motion vector recovery scheme, and experimented with standard video sequences. The experimental results show that our scheme restores original motion vector with more precision of 0.91 - 1.12 on average over conventional H.264 decoding with no error recovery.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.7
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• pp.52-60
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• 2008

The deblocking filter in the H.264/AVC video coding standard helps to reduce the blocking artifacts produced in the decoding process. But it consumes one third of the computational complexity in H.624/AVC decoder, which advocates an efficient design of a hardware accelerator for filtering. This paper proposes an architecture of deblocking filter using two filters and some registers for data reuse. Our architecture improves the throughput and minimize the number of external memory access by increasing data reuse. After initialization, two filters are able to perform filtering operation simultaneously. It takes only 96 clocks to complete filtering for one macroblock. We design and synthesis our architecture using Dongbuanam $0.18{\mu}m$ standard cell library and the maximum clock frequency is 200MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.8C
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• pp.720-728
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• 2007

For the improvement of coding efficiency, the H.264/AVC video coding standard employs new coding tools compared with existing coding standards. However, due to these new coding tools, the complexity of H.2641AVC encoder is greatly increased. Specially, Inter/Intra mode decision method of H.264/AVC using RDO(rate-distortion optimization) technique is one of the most complex parts in H.264/AVC. In this paper, we focus on the complexity reduction in macroblock mode decision considering coding efficiency. From the simulation results, the proposed algorithm reduce the encoding time by maximum 80% of total, and reduce the bitrate of the overall sequences by $8{\sim}10%$ on the average compared with existing coding methods.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.4 s.316
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• pp.8-16
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• 2007

For the improvement of coding efficiency, the H.264/AVC video coding standard employs new coding tools compared with existing coding standards. However, due to these new coding tools, the complexity of K264/AVC standard encoder is greatly increased. Specifically, the inter/intra mode decision method using RDO(rate-distortion optimization) technique is one of the most complex parts in H.264/AVC. In this paper, we focus on the complexity reduction in macroblock mode decision. In the proposed method, we reduce the complexity of the $4{\times}4$ mode decision process using $4{\times}4$ simple square filters, and using spatial block correlation method. Additionally, exploiting the best mode of sub_macroblock in $Inter8{\times}8$ mode, we proposed an algorithm to eliminate some intra modes in current macroblock mode decision process. In addition, we employed a method to raise the probability to select SKIP, $Intra16{\times}16$, and $Intra16{\times}16$ modes which usually show low complexity and low bitrate compared with other modes. From the simulation results, the proposed algorithm reduce the encoding time by maximum 83% of total, and reduce the bitrate of the overall sequences by $8{\sim}10%$ on the average compared with existing coding methods.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.8
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• pp.63-72
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• 2012

In this paper, we proposed a parallel architecture of line & block edge filter for high-performance H.264/AVC deblocking filter for Quad Full High Definition(Quad FHD) video real time processing. To improve throughput, we designed 4-parallel block edge filter with 16 line edge filter. To reduce internal buffer size and processing cycle, we scheduled 4-parallel zig-zag scan order as deblocking filtering order. To avoid data conflicts we placed 1 delay cycle between block edge filtering. We implemented interleaving buffer, as internal buffer of block edge filter, to sharing buffer for reducing buffer size. The proposed architecture was simulated in 0.18um standard cell library. The maximum operation frequency is 108MHz. The gate count is 140.16Kgates. The proposed H.264/AVC deblocking filter can support Quad FHD at 113.17 frames per second by running at 90MHz.