• Journal of the Institute of Electronics Engineers of Korea CI
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• v.44 no.3
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• pp.108-123
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• 2007

As H.264/AVC standard has proven to be a key technology of multimedia application, many researches to improve H.264/AVC standard are actively conducted. Those researches are conducted in various ways such as algorithm analysis and improvement or structure enhancement for reducing bottlenecks of performance. Even though targets and directions of those studies are not the same, performance of H.264/AVC standard is commonly analyzed in the early phase. In analysis phase, potential problems with H.264/AVC standard are identified and the most critical problem which has serious effects on performance is determined. Therefore, analysis phase is one of the important steps to decide overall directions and targets of the research. This research proposes a mathematical model which can be used in the early performance analysis phase to estimate performance in conducting research of improving the performance of H.264/AVC Baseline Profile decoder. The proposed model is designed by considering many variables of H.264/AVC decoder operation so that it is easy to predict its performance according to changes in each element.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.9A
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• pp.868-873
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• 2010

H.264/AVC video compression standard has been adopted for DMB, digital TV and various next generation broadcasting, communication and consumer electronics applications, and modern DVR system is also based on H.264/AVC standard. Although PC-based DVRs use PCI bus for main interface typically, H.264/AVC codec for SOCs use AHB bus for host interface. In this paper, we present an implementation of PCI to AHB interface module for H.264/AVC codec to efficiently communicate with a PC and experimental results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.12C
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• pp.1039-1045
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• 2008

The H.264/AVC video coding standard shows extremely higher coding efficiency, but it causes high computational complexity. Especially, the intra mode decision using the rate-distortion method requires many computations. Thus, the efficient intra mode decision methods have been proposed by decreasing the encoding complexity. In this paper, we propose an efficient intra mode decision algorithm using $4{\times}4$ integer transform coefficients in the conversion of MPEG-2 to H.264 standard. It is shown that the proposed algorithm reduces encoding time and complexity compared to the conventional algorithm, while showing similar PSNR performance.

• Proceedings of the IEEK Conference
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• 2009.05a
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• pp.225-227
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• 2009

International standard specification, H.264/SVC improved from H.264/AVC, is set up so as to promote free use of huge multimedia data in various channel environments.;H.264/AVC is a international standard speicification for video compression, adopted and commercialized as standard for DMB broadcasting by JVT of ISO/IEC MPEG and ITU-T VCEG. SVC standard uses 'intra/inter prediction' in AVC as well as 'inter-layer intra prediction', 'inter-layer motion prediction' and 'inter-layer residual prediction' to improve efficiency of encoding. Among prediction technologies, 'inter-layer intra prediction' is to use co-located block of up sampled sublevels as a prediction signal. At this time, application of interpolation is one of the most important factors to determine encoding efficiency. SVC's currently using poly-phase FIR filter of 4-tap and 2-tap respectively to luma components. This paper is written for the purpose of analyzing encoding performance according to the interpolation. For this purpose, we applied poly-phase FIR filter of '2-tap', '4-tap' and '6-tap' respectively to luma components and then measured bit-rate, PNSR and running time of interpolation filter. We're expecting that the analysis results of this paper will be utilized for effective application of interpolation filter. SVC standard uses 'intra/inter prediction' in AVC as well as 'inter-layer intra prediction', 'inter-layer motion prediction' and 'inter-layer residual prediction' to improve efficiency of encoding.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.11
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• pp.2020-2025
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• 2006

H.264/AVC is newest video coding standard of the ITU-T Video coding Experts Group and the ISO/IEC Moving Picture Expets Group. Recently H.264/AVC has been adopted as a video compression standard in DMB and multimedia equipments. In this paper, we propose a H.264/AVC intra frame decoder which can minimize the memory usage and chip size. The proposed intra frame decoder is described in VHDL language and simulated in model_sim. It was verified in chip level by downloading to XCV1000E FPGA chip.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.9C
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• pp.697-703
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• 2008

The H.264/AVC video coding standard provides higher coding efnciency compared to the conventional MPEG-2 standard. Since a lot of videos have been encoded using MPEG-2, the format conversion from MPEG-2 to H.264 is essential. In this paper, we propose an efficient method for the conversion of DCT coefficients to H.264/AVC transform coefficients. This conversion is essential, since $8{\times}8$ DCT and $4{\times}4$ integer transform are used in MPEG-2 and H.264/AVC, respectively. The mathematical analysis and computer simulation show that the computational complexity of the proposed algorithm is reduced compared to the conventional algorithm, while the loss caused by the conversion is negligible.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.10C
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• pp.805-812
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• 2008

H.264 technology is considered as the heart of the next-generation video codec standard. Europe and other countries have actually specified H.264 technology as the video codec standard for HD broadcasting. However, due to the complexity of algorithm, it is still a difficult job to implement HD-level H.264 decoders in real-time software. In this paper, I have restricted a part of the decoding process, in order to implement an H.264 software video decoder which guarantees a real-time operation, and suggest an H.264 decoder that adaptively selects the algorithm to minimize image degradation. Performance of the suggested H.264 decoder was compared and verified through a PC simulation. As a consequence, when the suggested decoder was used in an environment where real-time decoding was difficult, it has achieved the minimal image degradation as well as real-time decoding in most cases.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.45 no.5
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• pp.79-86
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• 2008

H.264/AVC is the newest international video coding standard developed by the joint ITU-T and ISO/IEC standards organizations. This newest video coding standard offers much higher coding efficiency than the H.261, H.263 and MPEG-4. But it has high computing complexity and high H/W resources wasting problem. This paper described the two unit parallel pipeline structure. This new structure comparing with standard model decreased the computing complexity of 67% and the H/W resources waste of 3%.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.8C
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• pp.729-737
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• 2007

The H.264/AVC video coding standard provides higher coding efficiency compared to the conventional MPEG-2 standard. Since a lot of videos have been encoded using MPEG-2, the format conversion from MPEG-2 to H.264 is essential. In this paper, we propose an efficient method for the conversion of DCT coefficients to H.264/AVC transform coefficients. This conversion is essential, since $8{\times}8$ DCT and $4{\times}4$ integer transform are used in MPEG-2 and H.264/AVC, respectively. The mathematical analysis and computer simulation show that the computational complexity of the proposed algorithm is reduced compared to the conventional algorithm, while the loss caused by the conversion is negligible.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.12
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• pp.50-56
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• 2016

This paper proposes the architecture and design of intra prediction circuit for a multi-decoder supporting UHD images. The proposed circuit supports not only the latest video compression standard HEVC but also H.264. In addition to the basic function of performing intra prediction, this circuit has the capability of performing the reference sample filter operation defined in the H.264 standard, and the smoothing and strong sample filter operations defined in the HEVC standard. We reduced the circuit size by sharing the circuit blocks for common operations and internal storage, and improved the circuit performance by parallel processing. The proposed circuit was described at RTL using Verilog HDL and its functionality was verified by using NC-Verilog of Cadence. The RTL circuit was synthesized by using Design Compiler of Synopsys and 130nm standard cell library. The synthesized gate-level circuit consists of 69,694 gates and processes 100 ~ 280 frames per second for 4K-UHD HEVC images at the maximum operation frequency of 157MHz.