• Title/Summary/Keyword: H.264 / AVC

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An Efficient Error Compensation Method for Thumbnail Extraction in H.264/AVC Bitstreams (H.264/AVC 비트스트림으로부터 썸네일 추출 시 효율적인 오차 보상 방법)

  • Yoon, Myung-Keun;Lee, Yeo-Song;Sohn, Chae-Bong;Park, Ho-Chong;Ahn, Chang-Beom;Oh, Seoung-Jun
    • Journal of Broadcast Engineering
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    • v.13 no.5
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    • pp.622-635
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    • 2008
  • Recently, high definition media services like HDTV and IPTV are growing. A fast reduced-size image extracting method is required to meet what those services require. Conventional DC image extracting methods, however, can't be applied to H.264/AVC streams since a spatial domain prediction scheme is adopted in H.264/AVC intra mode. To solve this problem, a thumbnail extraction method in H.264/AVC was proposed. However, the method has mismatch problem which was caused by round-off operation in intra prediction and mismatch between integer and floating point calculation. In this paper, we propose an error compensation method for extracting thumbnail directly in H.264/AVC bitstreams. The compensation method introduces the mismatch problem in thumbnail extraction and presents compensation values. Through the implementation and performance evaluation, proposed method compensated round-off error efficiently in D1 and HD sequences while the additional extraction time is negligible.

Low-power IP Design and FPGA Implementation for H.264/AVC Encoder (H.264/AVC Encoder용 저전력 IP 설계 및 FPGA 구현)

  • Jang, Young-Beom;Choi, Dong-Kyu;Han, Jae-Woong;Kim, Do-Han;Kim, Bee-Chul;Park, Jin-Su;Han, Kyu-Hoon;Hur, Eun-Sung
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.45 no.5
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    • pp.43-51
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    • 2008
  • In this paper, we are implemented low-power structure for Inter prediction, Intra prediction, Deblocking filter, Transform and Quantization blocks in H.264/AVC Encoder. The proposed Inter/Intra prediction blocks are shown 60.2% cell area reduction by adder reduction through Distributed Arithmetic, 44.3% add operation reduction using MUX for hardware share in Deblocking filter block. Furthermore we applied CSD and CSS process to reduce the cell area instead of multipliers that take a lot of area. The FPGA(Field Programmable Gate Array) and ARM Process based H.264/AVC encoder is implemented using proposed low power IPs. The proposed structure Platforms are implemented to interlock with FPGA and ARM processors. H.264/AVC Encoder implementation using Platforms shows that proposed low-power IPs can use H.264/AVC Encoder SoC effectively.

Advanced Fast Mode Decision Algorithm Applied to Inter Mode for H.264/AVC (H.264/AVC를 위해 inter mode에 적용된 향상된 고속 모드 결정 알고리즘)

  • Yang, Sang-Bong;Cho, Sang-Bock
    • Proceedings of the KIEE Conference
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    • 2007.04a
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    • pp.20-22
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    • 2007
  • The H.264/AVC standard developed by the joint Video Team (JVT) provides better coding efficiency than previous standards. The new emerging H.264/AVC employs variable block size motion estimation using multiple reference frame with 1/4-pel MV(Motion Vector) accuracy. These techniques are a important feature to accomplish higher coding efficiency. However, these techniques are increased overall computational complexity. To overcome this problem, this paper proposes advanced fast mode decision suited for variable block size by classifying inter mode based on Rate Distortion Optimization(RDO) technique. Proposed algorithm is going to use to implement H/W structure for fast mode decision. The experimental results shows that the proposed algorithm provides significant reduction computational complexity without any noticeable coding loss and additional computation. Entire computational complexity is decreased about 30%.

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A 4-parallel Scheduling Architecture for High-performance H.264/AVC Deblocking Filter (고성능 H.264/AVC 디블로킹 필터를 위한 4-병렬 스케줄링 아키텍처)

  • Ko, Byung-Soo;Kong, Jin-Hyeung
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.49 no.8
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    • pp.63-72
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    • 2012
  • In this paper, we proposed a parallel architecture of line & block edge filter for high-performance H.264/AVC deblocking filter for Quad Full High Definition(Quad FHD) video real time processing. To improve throughput, we designed 4-parallel block edge filter with 16 line edge filter. To reduce internal buffer size and processing cycle, we scheduled 4-parallel zig-zag scan order as deblocking filtering order. To avoid data conflicts we placed 1 delay cycle between block edge filtering. We implemented interleaving buffer, as internal buffer of block edge filter, to sharing buffer for reducing buffer size. The proposed architecture was simulated in 0.18um standard cell library. The maximum operation frequency is 108MHz. The gate count is 140.16Kgates. The proposed H.264/AVC deblocking filter can support Quad FHD at 113.17 frames per second by running at 90MHz.

New Motion Vector Prediction for Efficient H.264/AVC Full Pixel Motion Estimation (H.264/AVC의 효율적인 전 영역 움직임 추정을 위한 새로운 움직임 벡터 예측 방법 제안)

  • Choi, Jin-Ha;Lee, Won-Jae;Kim, Jae-Seok
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.44 no.3
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    • pp.70-79
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    • 2007
  • H.264/AVC has many repeated computation for motion estimation. Because of that, it takes much time to encode and it is very hard to implement into a real-time encoder. Many fast algorithms were proposed to reduce computation time but encoding quality couldn't be qualified. In this paper we proposed a new motion vector prediction method for efficient and fast full search H.264/AVC motion estimation. We proposed independent motion vector prediction and SAD share for motion estimation. Using our algorithm, motion estimation reduce calculation complexity 80% and less distortion of image (less PSNR drop) than previous full search scheme. We simulated our proposed method. Maximum Y PSNR drop is about 0.04 dB and average bit increasing is about 0.6%.

A Bitrate Control considering Interframe Variance of Image for H.264/AVC (화면간 영상 변화량을 고려한 H.264/AVC 비트율 제어 방법)

  • Son Nam-Rye;Lee Guee-Sang
    • The KIPS Transactions:PartB
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    • v.13B no.3 s.106
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    • pp.245-254
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    • 2006
  • In this work, a new rate control algorithm for transmission of H.264/AVC video bit stream through CBR(constant bit rate) channel is proposed. The proposed algorithm predicts target bit rate and MAD(mean of absolute difference) for current frame considering image complexity variance between neighboring backward and current images. In details, respective linear regression analysis for MAD and encoded bit rate against image complexity variance produce correlation parameters. Additionally, it uses frame skip technique to maintain bit stream within a manageable range and protect buffer from overflow or underflow. Implementation and experimental results show that the proposed algorithm can provide accurate bit allocation, and can effectively visual degradation after scene changes. Also our proposed algorithm encodes the video sequences with less frame skipping compared to the existing rate control for H.264/AVC.

Intra MB Prediction Mode Decision Method for Fast MPEG-2 to H.264/AVC Transcoding (고속 MPEG-2-H.264/AVC 변 환부호화를 위한 화면내 MB 예측 모드 결정 기법)

  • Liu, Xingang;Yoo, Kook-Yeol
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.33 no.12C
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    • pp.1046-1054
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    • 2008
  • Since the high quality digital TV systems are broadly deployed in the market, the digital video contents will be edited and distributed in MPEG-2 MP@HL fonnat. Due to its impressive coding efficiency, the H.264/AVC codec has rapidly replaced the MPEG-4 SP codec for mobile digital video terminal with low quality. For the bro ad distribution of digitial video contents produced in MPEG-2 format, the MPEG-2 to H.264/AVC transcoding is highly necessary nowadays. In this paper, we propose a fast intra MB prediction mode decision method to reduce the computational complexity in the transcoding, which is the main bottleneck in the transcoders. The proposed method is based on the several relationships such as DCT coefficients and edge orientation, correlation between prediction directions in the $Intra16{\times}16$ and $Intra4{\times}4$ modes, correlation between edge-orientations of luminance an d chrominance components. The simulation results show that the proposed method can reduce the computational complexity upto 70% and 40%, compared with the cascaded transcoder and the well-known fast intraframe transc oder, respectively.

Design of video encoder using Multi-dimensional DCT (다차원 DCT를 이용한 비디오 부호화기 설계)

  • Jeon, S.Y.;Choi, W.J.;Oh, S.J.;Jeong, S.Y.;Choi, J.S.;Moon, K.A.;Hong, J.W.;Ahn, C.B.
    • Journal of Broadcast Engineering
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    • v.13 no.5
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    • pp.732-743
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    • 2008
  • In H.264/AVC, 4$\times$4 block transform is used for intra and inter prediction instead of 8$\times$8 block transform. Using small block size coding, H.264/AVC obtains high temporal prediction efficiency, however, it has limitation in utilizing spatial redundancy. Motivated on these points, we propose a multi-dimensional transform which achieves both the accuracy of temporal prediction as well as effective use of spatial redundancy. From preliminary experiments, the proposed multi-dimensional transform achieves higher energy compaction than 2-D DCT used in H.264. We designed an integer-based transform and quantization coder for multi-dimensional coder. Moreover, several additional methods for multi-dimensional coder are proposed, which are cube forming, scan order, mode decision and updating parameters. The Context-based Adaptive Variable-Length Coding (CAVLC) used in H.264 was employed for the entropy coder. Simulation results show that the performance of the multi-dimensional codec appears similar to that of H.264 in lower bit rates although the rate-distortion curves of the multi-dimensional DCT measured by entropy and the number of non-zero coefficients show remarkably higher performance than those of H.264/AVC. This implies that more efficient entropy coder optimized to the statistics of multi-dimensional DCT coefficients and rate-distortion operation are needed to take full advantage of the multi-dimensional DCT. There remains many issues and future works about multi-dimensional coder to improve coding efficiency over H.264/AVC.

Watermark Implementation for Real-Time H.264/AVC Encoding (실시간 H.264/AVC 인코딩용 워터마크 구현)

  • Hong, You-Pyo;Won, Chee-Sun
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.34 no.7C
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    • pp.649-653
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    • 2009
  • Although digital image has many advantages including digital image compression and various image processing techniques, the it has the weakness of easy manipulation which led to the development of many digital watermarking techniques. There are various types of digital watermarking algorithms for spatial and spectral domains. This paper presents a watermarking implementation for H.264/AVC codec which is adapted for many multimedia standards.

Improved Rate-Distortion Estimation for Mode Decision in H.264/AVC (H.264/AVC에서 모드 결정을 위한 개선된 율-왜곡 예측)

  • Park, Ki-Hong;Kim, Yoon-Ho
    • Journal of Advanced Navigation Technology
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    • v.14 no.1
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    • pp.102-107
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    • 2010
  • This paper presented a rate-distortion estimation method for effective mode decision in H.264/AVC. In this approach, in order to decide a mode, laplacian distribution modeling of DCT coefficients is utilized, which do not need to such process as quantization, entropy coding. From the simulation results, proposed a method showed that rate-distortion between proposed scheme and practical value was almost the same and performed 0.02dB of PSNR gain.