• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.5
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• pp.2741-2761
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• 2017

With the purpose of copyright protection for digital video, a novel H.264/AVC watermarking algorithm based on JND model is proposed. Firstly, according to the characteristics of human visual system, a new and more accurate JND model is proposed to determine watermark embedding strength by considering the luminance masking, contrast masking and spatial frequency sensitivity function. Secondly, a new embedding strategy for H.264/AVC watermarking is proposed based on an analysis on the drift error of energy distribution. We argue that more robustness can be achieved if watermarks are embedded in middle and high components of $4{\times}4$ integer DCT since these components are more stable than dc and low components when drift error occurs. Finally, according to different characteristics of middle and high components, the watermarks are embedded using different algorithms, respectively. Experimental results demonstrate that the proposed watermarking algorithm not only meets the imperceptibility and robustness requirements, but also has a high embedding capacity.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.800-803
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• 2005

모바일 단말 기반 동영상 서비스 기술에 관한 연구는 최근에 이르기까지 활발히 수행되고 있으며, 인터넷 기반에서 상용화가 가능한 기술 분야를 모바일에 응용하는 시도가 계속되고 있다. 모바일 단말 기반 영상서비스와 관련하여 최신형 모바일 단말에서는 관련기술을 하드웨어적으로 구현하거나 독자적 동영상 압축기술을 적용한 소프트웨어적 구현을 통하여 동영상 서비스를 제공하고 있다. 그러나 상당한 비율을 점하고 있는 기존 모바일 단말에서는 이들 하드웨어 칩이 없거나 추가적으로 애드온(add-on) 할 수 있는 표준적인 방법이 정해지지 않아 최신의 동영상 서비스 기술을 제공받을 수 없다. 따라서 시시각각으로 변화하는 모바일 동영상 서비스 환경에 적극적으로 대처하기 위해서는 소프트웨어적 해결방안이 필수적이라는 인식이 대두되고 있다. 본 연구에서는 모바일 단말에서 소프트웨어 디코더를 이용하여 기존 단말에서 뿐만 아니라 향후 최신단말에서도 적극적으로 대처하기 위하여 H.264/AVC 기반 소프트웨어 디코더를 모바일 단말에 적용하는 방안에 대하여 제안한다.

• Journal of Information Processing Systems
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• v.11 no.3
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• pp.483-494
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• 2015

High Efficiency Video Coding (HEVC) is the most recent video codec standard of the ITU-T Video Coding Experts Group and the ISO/IEC Moving Picture Experts Group. The main goal of this newly introduced standard is for catering to high-resolution video in low bandwidth environments with a higher compression ratio. This paper provides a performance comparison between HEVC and H.264/AVC video compression standards in terms of objective quality, delay, and complexity in the broadcasting environment. The experimental investigation was carried out using six test sequences in the random access configuration of the HEVC test model (HM), the HEVC reference software. This was also carried out in similar configuration settings of the Joint Scalable Video Module (JSVM), the official scalable H.264/AVC reference implementation, running on a single layer mode. According to the results obtained, the HM achieves more than double the compression ratio compared to that of JSVM and delivers the same video quality at half the bitrate. Yet, the HM encodes two times slower (at most) than JSVM. Hence, it can be concluded that the application scenarios of HM and JSVM should be judiciously selected considering the availability of system resources. For instance, HM is not suitable for low delay applications, but it can be used effectively in low bandwidth environments.

• The Journal of the Korea Contents Association
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• v.9 no.4
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• pp.12-18
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• 2009

In this paper, we propose a novel method which efficiently codes $4{\times}4$ intra prediction modes in H.264/ AVC video encoding. There are nine optional prediction modes for each $4{\times}4$luma block and 4 modes for each $16{\times}16$luma block. To code each $4{\times}4$ intra prediction mode, lots of bits are required. To efficiently compress the intra mode bits in H.264/AVC, the most probable mode(MPM) is estimated by using the intra modes of the adjacent blocks, since intra modes for neighboring $4{\times}4$luma blocks are correlated. In this paper, a novel method for estimating the MPM is proposed by using the statistical distribution of intra modes of adjacent intra blocks. Experimental results show that the proposed method can achieve a coding gain of about 0.1dB.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.45 no.3
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• pp.142-148
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• 2008

Though a deblocking filter of H.264/AVC provides enhanced image quality by removing blocking artifact on block boundary, the complex filtering operation on this process is a dominant factor of the whole decoding time. In this paper, we designed an ASIP to accelerate deblocking filter operation with the proposed instruction set. We designed a processor based on a MIPS structure with LISA, simulated a deblocking later model, and compared the execution time on the proposed instruction set. In addition, we generated HDL model of the processor through CoWare's Processor Designer and synthesized with TSMC 0.25um CMOS cell library by Synopsys Design Compiler. As the result of the synthesis, the area and delay time increased 7.5% and 3.2%, respectively. However, due to the proposed instruction set, total execution performance is improved by 18.18% on average.

• Journal of Broadcast Engineering
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• v.16 no.6
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• pp.996-1008
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• 2011

This paper proposes a PSNR estimation algorithm of H.264/AVC bitstream for hierarchical B-picture structure. The proposed method consists of a modeling method for DCT coefficients for I-pictures and an error estimation method for blocks encoded by skip mode. The modeling method selects an appropriate model between Laplacian and Cauchy model, and the error of skip mode is estimated from MSE values of reference pictures. Experimental results show that the modeling method predicts more accurate PSNR values than Laplacian and Cauchy model and the error estimation method of skip mode enhances PSNR estimation of hierarchical B-picture structure.

• Journal of Broadcast Engineering
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• v.14 no.2
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• pp.219-227
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• 2009

In H.264/AVC, if each block is quantized with a adaptive quantization parameter(QP) regardless of the characteristics of a block, it could be the deterioration of the picture quality. In this paper, an adaptive block-based QP selection method is proposed in order to improve picture quality by utilizing the bit amounts of the zigzag-scanned integer transform coefficients of the neighboring blocks and changing the QP value in the current block. The proposed method works in the same way as the encoder and decoder without transmitting the change of QP value to the decoder side. The experimental results show that the proposed method achieves a gain of about $0.1\sim0.3dB$ compared with H.264/AVC.

• Journal of Korea Multimedia Society
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• v.13 no.2
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• pp.185-195
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• 2010

In this paper, we propose an efficient inter and intra prediction algorithms for fast encoding of H.264/AVC. First, inter prediction mode decision method decides early using temporal/spatial correlation information and pixel direction information. Second, intra prediction mode decision method selects block size judging smoothness degree with inner/outer pixel value variation and decides prediction mode using representative pixel and reference pixel. Lastly, adaptive motion search region restriction sets search region using mode information of neighboring block and predicted motion vector. The experimental results show that proposed method can achieve about 18~53% reduction compared with the existing JM 14.1 in the encoding time. In RD performance, the proposed method does not cause significant PSNR value losses while increasing bitrates slightly.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.11
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• pp.2503-2510
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• 2012

This paper proposes a parallel operation intra predictor for H.264/AVC decoder. In previous intra predictor design, common operation units were designed for 17 prediction modes in order to compute more effectively. However, it was designed by analyzing the equation applied to one pixel. So, there are four operation units for computing 16 pixels in a $4{\times}4$ block and they need four cycles. In this paper, the proposed intra predictor contains T3(Three Type Transform) operation unit for parallel operation. It divides 17 modes into 3 types to calculate 16 pixels of a $4{\times}4$ block in only one cycle and needs 16 cycles minimum in 16x16 block. As the result of the experiment, in terms of processing cycle, the performance of proposed intra predictor is 58.95% higher than the previous one.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.71-78
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• 2008

In this paper, we implement the H.264/AVC baseline decoder by hardware-software partitioning under the embedded Linux Kernel 2.4.26 and the FPGA-based target board with ARM926EJ-S core. We design several IPs for the time-demanding blocks, such as motion compensation, deblocking filter, and YUV-to-RGB and they are communicated with the host through the AMBA bus protocol. We also try to minimize the number of memory accesses between IPs and the reference software (JM 11.0) which is ported in the embedded Linux. The proposed IPs and the system have been designed and verified in several stages. The proposed system decodes the QCIF sample video at 2 frame per second when 24MHz of system clock is running and we expect the bitter performance if the proposed system is designed with ASIC.