• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.3
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• pp.21-29
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• 2012

This paper presents optimized searching technique to improve the performance of H.264/AVC. By using the proposed forward and backward searching algorithm, redundant cycles of latency for data reordering can be removed. Furthermore, in order to reduce the total number of execution cycles of CAVLC encoder, early termination mode and two stage pipelined architecture are proposed. The experimental result shows that the proposed architecture needs only 36.0 cycles on average for each $16{\times}16$ macroblock encoding. The proposed architecture improves the performance by 57.8% than that of previous designs. The proposed CAVLC encoder was implemented using Verilog HDL and synthesized with Magnachip $0.18{\mu}m$ standard cell library. The synthesis result shows that the gate count is about 17K with 125Mhz clock frequency.

• Journal of Broadcast Engineering
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• v.13 no.5
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• pp.732-743
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• 2008

In H.264/AVC, 4$\times$4 block transform is used for intra and inter prediction instead of 8$\times$8 block transform. Using small block size coding, H.264/AVC obtains high temporal prediction efficiency, however, it has limitation in utilizing spatial redundancy. Motivated on these points, we propose a multi-dimensional transform which achieves both the accuracy of temporal prediction as well as effective use of spatial redundancy. From preliminary experiments, the proposed multi-dimensional transform achieves higher energy compaction than 2-D DCT used in H.264. We designed an integer-based transform and quantization coder for multi-dimensional coder. Moreover, several additional methods for multi-dimensional coder are proposed, which are cube forming, scan order, mode decision and updating parameters. The Context-based Adaptive Variable-Length Coding (CAVLC) used in H.264 was employed for the entropy coder. Simulation results show that the performance of the multi-dimensional codec appears similar to that of H.264 in lower bit rates although the rate-distortion curves of the multi-dimensional DCT measured by entropy and the number of non-zero coefficients show remarkably higher performance than those of H.264/AVC. This implies that more efficient entropy coder optimized to the statistics of multi-dimensional DCT coefficients and rate-distortion operation are needed to take full advantage of the multi-dimensional DCT. There remains many issues and future works about multi-dimensional coder to improve coding efficiency over H.264/AVC.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.5C
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• pp.371-381
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• 2005

In this paper, we propose an advanced hardware architecture for the CAVLC entropy encoder/decoder engine for real time video compression. The CAVLC (Context-based Adaptive Variable Length Coding) is a lossless compression method in H.264/AVC and it has high compression efficiency but has computational complexity. The reference memory size is optimized using partitioned storing method and memory reuse method which are based on partiality of memory referencing. We choose the hardware architecture which has the most suitable one in several encoder/decoder architectures for the mobile devices and improve its performance using parallel processing. The proposed architecture has been verified by ARM-interfaced emulation board using Altera Excalibur and also synthesized on Samsung 0.18 um CMOS technology. The synthesis result shows that the encoder can process about 300 CIF frames/s at 150MHz and the decoder can process about 250 CIF frames/s at 140Mhz. The hardware architectures are being used as core modules when implementing a complete H.264/AVC video encoder/decoder chip for real-time multimedia application.

• Proceedings of the Korea Information Processing Society Conference
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• 2014.11a
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• pp.971-974
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• 2014

H.264/AVC 영상 부호화기의 비트율(Bitrate) 제어에 사람의 눈에 잘 인식되는 부분의 화질을 향상하고 인식률이 낮은 부분의 화질을 낮추어 상대적으로 향상된 화질을 얻기 위한 방법을 연구하였다. 먼저 H.264/AVC 영상 부호화기에서, 장면 변화로 인한 참조 프레임의 비트 낭비를 막기 위해 GOP(Group of Pictures) 단위로 장면 변화를 검출한 후, 검출된 장면 변화에 대해 GOP를 적용 시킨다. 해당 GOP 내에서 시각 인지도에 기초하여 물체의 움직임으로 인한 인식률이 높은 부분을 검출하고, 인식률이 높은 부분에 대해 QP(Quantization Parameter)의 재분배로 비트율을 높임으로써 화질을 향상시키고, 인식률이 낮은 부분에 대해서는 비트율을 적게 분배한다. 그 결과 한정된 대역폭을 갖는 전송 환경에서 영상을 향상된 화질로 이용할 수 있는 방법을 제안한다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.34-40
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• 2010

This paper proposes an efficient CABAC encoder to reduce syntax element storage in H.264/AVC entropy coding. In the proposed architecture, all blocks are designed in dedicated hardware, so it performs fast processing without programmable processors. Context modeler of CABAC encoder requires the neighbor block data. However it requires impractically huge memory size if the neighbor block data is directly stored without proper processing. Therefore, this paper proposes an effective method of storing the neighbor block data to decrease memory size. The proposed CABAC encoder has 35,463 gates in 0.18um standard cell library. It operates at maximum speed of 180MHz and its throughput is about 1 cycle per input symbol.

• Journal of Broadcast Engineering
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• v.17 no.3
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• pp.471-479
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• 2012

Intra prediction is one of the significant techniques in H.264/AVC reference software; however, it has heavy computational complexity. In order to solve this problem, many fast algorithms have been proposed. In this paper, we propose a fast intra mode decision algorithm which predicts the edge direction of the current block using sub-sampled pixels to reduce high computational complexity of the H.264/AVC encoder. The proposed algorithm shows that it not only improves the coding performance but also reduces the computational complexity of the H.264/AVC encoder compared to previous algorithms. The experimental results show that the proposed algorithm achieves the encoding time reduction of 75.93% on an average with slight peak signal-to-noise ratio (PSNR) drop and bit-rate increment.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.3C
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• pp.250-257
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• 2006

In this paper, we propose an efficient algorithm for the RDO mode decision in H.264/AVC encoder. Based on the properties of DCT coefficients and the RDO mode decision processing, we derive a new condition for detecting an error block having all-zero DCT coefficient (AZCB). (I)DCT, (I)Q, and entropy coding are skipped for AZCBs in the proposed algorithm. It makes the reduction of the computational complexity for the RDO mode decision. Simulation results show that the proposed algorithm achieves computational saving over 40% compared to the conventional method.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.11
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• pp.2285-2291
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• 2011

In this paper, H.264 high profile intra frame encoder, which integrates intra prediction, context-based adaptive variable length coding(CAVLC), and DDR2 memory control module, is proposed. The designed encoder can be operated in 440 cycle for one-macroblock. In order to verify the encoder function, we developed the reference C from JM 13.2 and verified the developed hardware using test vector generated by reference C. The designed encoder is verified in the FPGA (field programmable gate array) with operating frequency of 200 MHz for DMA (direct memory access), operating frequency of 50 MHz of Encoder module, and 25 MHz for VIM(video input module). The number of LUT is 43099, which is about 20 % of Virtex 5 XC5VLX330.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.66-72
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• 2009

This paper proposes an efficient binary arithmetic encoder for CABAC which is used one of the entropy coding methods for H.264/AVC. The present binary arithmetic encoding algorithm requires huge complexity of operation and data dependency of each step, which is difficult to be operated in fast. Therefore, renormalization exploits 2-stage pipeline architecture for efficient process of operation, which reduces huge complexity of operation and data dependency. Context model updater is implemented by using a simple expression instead of transIdxMPS table and merging transIdxLPS and rangeTabLPS tables, which decreases hardware size. Arithmetic calculator consists of regular mode, bypass mode and termination mode for appearance probability of binary value. It can operate in maximum speed. The proposed binary arithmetic encoder has 7282 gate counts in 0.18um standard cell library. And input symbol per cycle is about 1.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2006.07a
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• pp.406-406
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• 2006