• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.10
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• pp.56-65
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• 1999

This paper presents an architecture and its instruction set for a graphic coprocessor(GCP) which can be used for a multimedia server. The proposed instruction set employs parallel architecture concepts, such as SIMD and Superscalar. GCP consists of a scheduler and four functional units. The scheduler solves an instruction bottleneck problem causing by sharing with four general processors(GPs). GCP can execute up to 4 instructions in parallel. It consists of about 56,000 gates and operates at 30 MHz clock frequency due to speed limitation of SOG technology. GCP meets the real-time DCT algorithm requirement of the CIF image format and can process up to 63 frames/sec for the DCT Algorithm and 21 frames/sec for the Full Block matching Algorithm of the CIF image format.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.1
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• pp.25-37
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• 1996

To process computer graphics in real time, the high-speed operations(multiplier and adder) are needed to increase the speed of graphic process. RNS(Residue Number System) is integer number system that has the parallel and high-speed operation. Also, it is able to design both high-speed multiplier and adder, since a cyclic group has an isomorphic relation between multiplication and addition in RNS. So in this paper, DRNS(Double Residue Number System) is proposed, it is used for the multiplier and the adder, which are designed using a circulative code for the high-speed graphic processor in RNS. The designed multiplier would operate with the speed of 87Mzz two TTL using 74s09 and 74s32.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.38 no.3
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• pp.217-227
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• 1989

A process control graphic system is proposed as an efficient tool for monitoring the operation of power plant. It uses the multi-processor structure with 60 Kbyte shared memory as an implemental type of the distributed computer system, so that it is flexible, functionally extensible, and applicable to real-time process. The shared memory is used as a real-time database handling the process values and operator's commands. The database files, generated by the user-interactive graphic editor developed for the system or text editor, have the characteristics of simplicity and user-friendliness. The process control graphic system, that can monitor the operation of boiler and function as a backup controller in case of failure in boiler controller, is applied to Ulsan power plant. As a result, it displays the operating data of the boiler process without error by 14 pages of color graphic image according to the operation menu, and additionally functions well as a fault-tolerant control system.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.7
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• pp.1276-1280
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• 2009

This paper presents a fault diagnosis expert system for 765kV substation. The proposed system includes the topology processor and intelligent alarm processing subsystems. This expert system estimates the fault section through the inference process using heuristic knowledge and the output of topology processor and intelligent alarm processing system. The rule-base of this expert system is composed of basic rules suggested by Korea Electric Power Corporation and heuristic rules. This expert system is developed using PROLOG language. Also, user friendly Graphic User Interface is developed using visual basic programming in the windows XP environment. The proposed expert system showed a promising performance through the several case studies.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.5
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• pp.1-11
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• 1994

In computer graphics since objects atre constructed by lines and curves, the high-speed curve generator is indispensible for computer aided design and simulatation. Since the functions of graphic generation can be represented as a series of matrix operations, in this paper, two kind of the high-speed Bezier curve generator that uses matrix equation and a recursive relation for Bezier polynomials are designed. And B-spline curve generator is designed using interdependence of B-spline blending functions. As the result of the comparison of designed curve generator and reference [5], [6] in the operation time and number of operators, the curve generator with 1-dimensional systolic array processor for matrix vector operation that uses matrix equation for Bezier curve is more effective.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.29 no.1 s.232
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• pp.96-106
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• 2005

An integrated single-wafer processing tool, composed of multiple single wafer processing modules, transfer robots, and load locks, has complex routing sequences, and often has critical post-processing residency constraints. Scheduling of these tools is an intricate problem, and testing schedulers with actual tools requires too much time and cost. The Single Wafer Processor (SWP) simulator presented in this paper is to validate an on-line scheduler, and evaluate performance of integrated single-wafer processing tools before the scheduler is actually deployed into real systems. The data transfer between the scheduler and the simulator is carried out with TCP/IP communication using messages and files. The developed simulator consists of six modules, i.e., GUI (Graphic User Interface), emulators, execution system, module managers, analyzer, and 3D animator. The overall framework is built using Microsoft Visual C++, and the animator is embodied using OpenGL API (Application Programming Interface).

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.3
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• pp.345-350
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• 1986

This paper deseribes the design of a vector-coordinate rotation processor and the apporoximate evaluations of sine and consine based upon the use of residue number systems. The proposed algorithm results in a considerable improvement of computational speed as compared to the CORDIC algorithm. According to the results of computer simulation, the mean error of sine and cosine is 0.0025, and the mean error of coorcinate rotation arithmatic is 0.65. The proposed processor has the efficiency for the design and fabrication of integrated circuits, because it consists of an array of identical lookup tables.

• Journal of computational fluids engineering
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• v.21 no.2
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• pp.25-31
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• 2016

In this paper, a study on the development of OpenFOAM grid generation program for two-dimensional flow analysis is described. By using the pre-processor(eMEGA) of EDISON_CFD system, grids for OpenFOAM flow calculation were obtained. Resultant two-dimensional grids were used to calculate flow fields by applying simpleFoam, one of the OpenFOAM's popular solvers, and the obtained flow results were compared with theoretical and experimental data available. Also grids generated by present program were compared with grids by a commercial pre-processor Pointwise for the purpose of verification. Verification work includes three cases(single block, O-type single block, and multi block grid), and all results show reasonable matches. According to the current achievement, it can be concluded that OpenFOAM grid can be constructed conveniently by using eMEGA with GUI.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.19 no.4
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• pp.119-128
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• 2019

Due to the nature of the 3D graphics processor system, many mathematical calculations are required and parallel processing research using GPU (Graphics Processing Unit) is being performed for high-speed processing. In this paper, we propose a 3D graphics processor using MAMS, a parallel processor that does not use cache memory, to solve the GPU problem of increasing bandwidth caused by cache memory miss and the problem that 3D shader processing speed is not constant. The 3D graphics processor using MAMS proposed in this paper designed Vertex shader, Pixel shader, Tiling and Rasterizing structure using DirectX command analysis, the FPGA(Xilinx Virtex6@100MHz) board for MAMS was constructed and designed using Verilog. We compared the processing time of the developed FPGA (100Mhz) and nVidia GeForce GTX 660 (980Mhz), the processing time using GTX 660 was not constant and suing MAMS was constant.

• The KIPS Transactions:PartA
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• v.19A no.2
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• pp.73-76
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• 2012

In this paper, we propose an efficient method to extract surface atoms from a protein molecule. Surface atoms are defined as a set of atoms who can contact given probe solvent $P$, where $P$ does not collide with the molecule. The atoms contained in the molecule are represented as a set of spheres with van der Waals radii. The probe solvent also is represented as a sphere. We propose a method to extract the surface atoms by computing the offset surface of the molecule with respect to the radius of $P$. For efficient computation of the offset surface of a molecule, a voxel map is constructed for the offset surfaces of the spheres. Based on GPU (graphic processor unit) acceleration, a data parallel algorithm is used to extract the surface atoms in 42.87 milliseconds for the molecule containing up to 6,412 atoms.