• Title/Summary/Keyword: Graphic processor

Search Result 119, Processing Time 0.027 seconds

Developemtn of Vehicle Dynamics Program AutoDyn7(II) - Pre-Processor and Post-Processor (차량동역학 해석 프로그램 AutoDyn7의 개발(∥) - 전처리 및 후처리 프로그램)

  • 한종규;김두현;김성수;유완석;김상섭
    • Transactions of the Korean Society of Automotive Engineers
    • /
    • v.8 no.3
    • /
    • pp.190-197
    • /
    • 2000
  • A graphic vehicle modeling pre-processing program and a visualization post-processing program have been developed for AutoDyn7, which is a special program for vehicle dynamics. The Rapid-App for GUI(Graphic User Interface) builder and the Open Inventor for 3D graphic library have been employed to develop these programs in Silicon Graphics workstation. A Graphic User Interface program integrates vehicle modeling pre-processor, AutoDyn7 analysis processor, and visualization post-processor. In vehicle modeling pre-processor, vehicle hard point data for a suspension model are automatically converted into multibody vehicle system data. An interactive graphics capabilities provides suspension modeling aides to verify user input data interactively. In visualization post-processor, vehicle virtual test simulation results are animated with virtual testing environments.

  • PDF

Design of a Graphic Accelerator uisng 1-Dimensional Systolic Array Processor for Matrix.Vector Opertion (행렬 벡터 연사용 1-차원 시스톨릭 어레이 프로세서를 이용한 그래픽 가속기의 설계)

  • 김용성;조원경
    • Journal of the Korean Institute of Telematics and Electronics B
    • /
    • v.30B no.1
    • /
    • pp.1-9
    • /
    • 1993
  • In recent days high perfermance graphic operation is needed, since computer graphics is widely used for computer-aided design and simulator using high resolution graphic card. In this paper a graphic accelerator is designd with the functions of graphic primitives generation and geometrical transformations. 1-D Systolic Array Processor for Matris Vector operation is designed and used in main ALU of a graphic accelerator, since these graphic algorithms have comonon operation of Matris Vector. Conclusively, in case that the resolution of graphic domain is 800$\times$600, and 33.3nsec operator is used in a graphic accelerator, 29732 lines per second and approximately 6244 circles per second is generated.

  • PDF

Development of a High-speed Color Graphic Processor with a Real-time Image processing Capability (실시간 영상처리 기능을 갖는 고속 칼라 그래픽 프로세서의 개발)

  • Bien, Zeung-Nam;Oh, Sang-Rtok;Jang, Won;You, Bum-Jae;Park, Jong-Cheol;Ha, Kyung-Ho
    • Proceedings of the KIEE Conference
    • /
    • 1990.11a
    • /
    • pp.443-445
    • /
    • 1990
  • In this paper, a high speed graphic processor module with a real-time processing capability is proposed, where the module is design to be compatible to the standard VME bus and consists of TMS34010 Graphic processor, TMS44C251 frame buffer, 512KB system memory and BT101 digital to analog converter. The proposed graphic module is implemented and tested in real-time via experiments with an integrated system with other VME modules.

  • PDF

Design of Graphic Generator for Driving HUD(Head-Up Display) and MFD(Multi-Function Display) (전방시현기 및 다기능시현기 구동을 위한 그래픽 영상생성기 설계 연구)

  • 황상현;이재억;박덕배
    • Journal of the Korea Institute of Military Science and Technology
    • /
    • v.5 no.2
    • /
    • pp.72-82
    • /
    • 2002
  • This paper presents the design technology of a Graphic Generator which drives the embedded aircraft display equipments such as HUD(Head-Up Display) and MFD (Multi-Function Display) those provide pilot with the most important mission information. The main issue of this design is how we can implement the real-time embedded graphic generator using a general purpose processor as a substitute for the obsolete the production of specific graphic processor in the military market. So we proposed two kinds of method that one is a software solution so called graphic kernel system, interpreting the display file, controlling the graphic system and pre-processing graphic primitives, the other is a hardware solution so called graphic engine, interpreting passed commands through the graphic kernel system, post-processing the looping calculation taking much of time as implemented by software. We have tested and verified the functionalities and the required performance of Graphic Generator.

Acceleration for Removing Sea-fog using Graphic Processors and Parallel Processing (그래픽 프로세서를 이용한 병렬연산 기반 해무 제거 고속화)

  • Kim, Young-doo;Kwak, Jae-min;Seo, Young-ho;Choi, Hyun-jun
    • Journal of Advanced Navigation Technology
    • /
    • v.21 no.5
    • /
    • pp.485-490
    • /
    • 2017
  • In this paper, we propose a technique for high speed removal of sea-fog using a graphic processor. This technique uses a host processor(CPU) and several graphics processors(GPU) capable of parallel processing to remove sea-fog from the input image. In the process of removing sea-fog, the dark channel extraction, the maximum brightness channel extraction, and the calculation of the transmission are performed by the host processor, and the process of refining the transmission by applying the bidirectional filter is performed in parallel through the graphic processor. To verify the proposed parallel processing method, three NVIDIA GTX 1070 GPUs were used to construct the verification environment. As a result, it takes about 140ms when implemented with one graphics processor, and 26ms when implemented using OpenMP and multiple GPGPUs. The proposed a parallel processing algorithm based on the graphics processor unit can be used for safe navigation, port control and monitoring system.

Development of a Graphic User Interface Program for Suspension Design (현가장치 설계용 그래픽 사용자 접속 프로그램 개발)

  • Kim, H.K.;Yoo, H.H.;Choi, K.R.;Lee, M.S.
    • Transactions of the Korean Society of Automotive Engineers
    • /
    • v.6 no.6
    • /
    • pp.7-14
    • /
    • 1998
  • A graphic user interface program for the design of vehicle suspension system is developed in this work. Graphic templates are designed by using a graphic language and a library and given to users for interactive data input. Several suspension types are graphically given, and the information of hard points can be directly provided on the graphic templates by users. The information is saved in a data structure which can be efficiently accessed, and transformed into another data format. The data transformation is for the interface to an analyzer by which suspension design characteristics can be calculated.

  • PDF

The Need of Cache Partitioning on Shared Cache of Integrated Graphics Processor between CPU and GPU (내장형 GPU 환경에서 CPU-GPU 간의 공유 캐시에서의 캐시 분할 방식의 필요성)

  • Sung, Hanul;Eom, Hyeonsang;Yeom, HeonYoung
    • KIISE Transactions on Computing Practices
    • /
    • v.20 no.9
    • /
    • pp.507-512
    • /
    • 2014
  • Recently, Distributed computing processing begins using both CPU(Central processing unit) and GPU(Graphic processing unit) to improve the performance to overcome darksilicon problem which cannot use all of the transistors because of the electric power limitation. There is an integrated graphics processor that CPU and GPU share memory and Last level cache(LLC). But, There is no LLC access rules between CPU and GPU, so if GPU and CPU processes run together at the same time, performance of both processes gets worse because of the contention on the LLC. This Paper gives evidence to prove the need of the Cache Partitioning and is mentioned about the cache partitioning design using page coloring to allocate the L3 Cache space only for the GPU process to guarantee GPU process performance.

Design and Implementation of Hangul Graphic Board to Speed up the Generation of High Resolution Fonts used in Electric Public System (전자 출판 시스템에 사용되는 고해상도 문자의 발생을 가속시키기 위한 한글 그래픽 보드의 설게 및 제작)

  • 황규철;경종민
    • Journal of the Korean Institute of Telematics and Electronics
    • /
    • v.27 no.5
    • /
    • pp.802-807
    • /
    • 1990
  • In this thesis, we represent the study on the design and implementation of the hangul graphic board which generate bit map font data from the boundary information of korean or chines fonts. The implemented graphic board consists of a TMS34010 Graphic System Processor (GSP) and two TMS320C25 Digital Signal Processor (DSP), and there is shared memory which consists of two memory blocks with same address for which is possible parallel processing between two processors. And in using DSP, we propose an efficient algorithm for calculation of Bezier curve which require much times to calculate bit map data font from the boundary information.

  • PDF

Multi-Port Register File Design and Implementation for the SIMD Programmable Shader (SIMD 프로그래머블 셰이더를 위한 멀티포트 레지스터 파일 설계 및 구현)

  • Yoon, Wan-Oh;Kim, Kyeong-Seob;Cheong, Jin-Ha;Choi, Sang-Bang
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.45 no.9
    • /
    • pp.85-95
    • /
    • 2008
  • Characteristically, 3D graphic algorithms have to perform complex calculations on massive amount of stream data. The vertex and pixel shaders have enabled efficient execution of graphic algorithms by hardware, and these graphic processors may seem to have achieved the aim of "hardwarization of software shaders." However, the hardware shaders have hitherto been evolving within the limits of Z-buffer based algorithms. We predict that the ultimate model for future graphic processors will be an algorithm-independent integrated shader which combines the functions of both vertex and pixel shaders. We design the register file model that supports 3-dimensional computer graphic on the programmable unified shader processor. we have verified the accurate calculated value using FPGA Virtex-4(xcvlx200) made by Xilinx for operating binary files made by the implementation progress based on synthesis results.

Control Unit Design and Implementation for SIMD Programmable Unified Shader (SIMD 프로그래머블 통합 셰이더를 위한 제어 유닛 설계 및 구현)

  • Kim, Kyeong-Seob;Lee, Yun-Sub;Yu, Byung-Cheol;Jung, Jin-Ha;Choi, Sang-Bang
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.48 no.7
    • /
    • pp.37-47
    • /
    • 2011
  • Real picture like high quality computer graphic is widely used in various fields and shader processor, a key part of a graphic processor, has been advanced to programmable unified shader. However, The existing graphic processors have been optimized to commercial algorithms, so development of an algorithm which is not based on it requires an independent shader processor. In this paper, we have designed and implemented a control unit to support high quality 3 dimensional computer graphic image on programmable integrated shader processor. We have done evaluation through functional level simulation of designed control unit. Hardware resource usage rate are measured by implementing directly on FPGA Virtex-4 and execution speed are verified by applying ASIC library. the result of an evaluation shows that the control unit has the commands more about 1.5 times compared to the other shader processors that is a behavior similar to the control unit and with a number of processing units used in a shader processor, compared with the other processors, overall performance of the control unit is improved about 3.1 GFLOPS.