• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2002년도 추계학술대회 논문집
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• pp.616-619
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• 2002

The z-map structure is widely used for NC tool path verification as it is very simple and fast in calculation of Boolean operations. However, if the number of the x-y grid points in a z-map is increased to enhance its accuracy, the computation time for NC verification increases rapidly. To reduce this computation time, we proposed a NC verification method using 3-D graphic acceleration hardwares. In this method, the z-map of the resultant workpiece machined by a NC program is obtained by rendering tool swept volumes along tool pathos and reading the depth buffer of the graphic card. The experimental results show that this hardware-based method is faster than the conventional software-based method.

• 한국정보과학회논문지:시스템및이론
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• 제33권11호
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• pp.853-858
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• 2006

본 논문에서는 깊이 영상기반의 3차원 그래픽 객체에 대하여 그래픽 처리 장치(Graphics Processing Unit, GPU)의 가속을 이용한 고속의 렌더링 기법을 제안한다. 제안하는 알고리즘은 최근의 그래픽 처리 장치의 새로운 특징과 프로그래밍이 가능한 쉐이더 기법을 이용하여, 속도가 느리거나 정적인 조명과 같은 기존의 일반적인 깊이 영상기반 렌더링 방법이 갖고 있는 단점을 극복할 수 있다. 깊이 영상기반 데이타의 3차원 변환 및 조명에 의한 효과 연산은 정점 쉐이더(vertex shader)에서 수행을 하고, 점 데이타의 적응적인 스플래팅(splatting)은 화소 쉐이더(fragment shader)에서 수행된다. 모의 실험결과, 소프트웨어 렌더링 또는 OpenGL 기반의 렌더링과 비교해서 괄목할 만한 렌더링 속도의 향상이 이루어졌다.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2003년도 ICCAS
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• pp.2116-2120
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• 2003

A frame buffer device is an abstraction for the graphic hardware. It allows application software to access the graphic hardware through a well-defined interface, so that the software doesn’t need to know anything about the low-level interface stuff. We develop a frame buffer driver for VIA’s CLE266 graphic system based on ‘Qplus’, an embedded linux operating system developed by ETRI. Then, it will be seen that our frame buffer system is applied to embedded solutions such as movie player and X server successfully.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2000년도 제15차 학술회의논문집
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• pp.120-120
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• 2000

In this study, in order to control real system under the environment of graphic user interface, study on the technique which can control real system without additional hardware drivers using virtual machine driver operated on the windows operating system. Consider the problem which is the error and the delay of a sampling time on the multi task processing through the load test of the experiment using graphic user interface.

• 한국정보통신학회논문지
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• 제14권12호
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• pp.2675-2680
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• 2010

3D 그래픽을 처리하는 연산 과정에는 고정적인 연산만을 수행하는 영역과 Shader 등과 같은 명령어에 의한 프로그래밍이 요구되는 영역이 구분되어 있다. 이러한 3D 파이프라인의 특성을 고려하여 fixed 구조로 설계한 graphics hardware와 명령어 기반의 programmable hardware를 혼합한 구조로 설계하면 효율적인 그래픽 처리가 가능하다. 본 논문에서는 이러한 혼합 구조에 적합한 OpenGL ES(Open Graphics Library Embedded System) 2.0을 지원하는 Fragment Shader를 설계하였다. fixed hardware와 Shader간 데이터 입출력으로 인해 발생할 수 있는 전체 파이프라인의 지연을 줄일 수 있도록 내부 인터페이스를 최적화하였으며 Shader 내부 레지스터 그룹을 interleaved 구조로 설계하여 레지스터 면적과 처리 속도를 개선하였다.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1993년도 한국자동제어학술회의논문집(국제학술편); Seoul National University, Seoul; 20-22 Oct. 1993
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• pp.288-292
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• 1993

This paper summerizes a prototype central control system of distribution automation system, which is a result of project carried out by KERI and 6 companies. Of the many possible systems, feeder automation oriented system is described. Control hardware system is composed of one super-mini and 2 workstations. Two kinds of commercial softwares, DBMS and graphic tools, are adopted. Three component system of the hardware has its own role, host system for DB managent, F.A. program running, communication scheduling, and etc., two workstations for communication node and graphic interface node. System management program, feeder automation program including load forcasting, communication scheduling and supervisory contorl functions are developed on the basis of above hardware and properly designed protocol, communication system and terminals.

• 한국군사과학기술학회지
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• 제5권2호
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• pp.72-82
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• 2002

This paper presents the design technology of a Graphic Generator which drives the embedded aircraft display equipments such as HUD(Head-Up Display) and MFD (Multi-Function Display) those provide pilot with the most important mission information. The main issue of this design is how we can implement the real-time embedded graphic generator using a general purpose processor as a substitute for the obsolete the production of specific graphic processor in the military market. So we proposed two kinds of method that one is a software solution so called graphic kernel system, interpreting the display file, controlling the graphic system and pre-processing graphic primitives, the other is a hardware solution so called graphic engine, interpreting passed commands through the graphic kernel system, post-processing the looping calculation taking much of time as implemented by software. We have tested and verified the functionalities and the required performance of Graphic Generator.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 추계학술대회 논문집 전력기술부문
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• pp.127-130
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• 2002

Recently, with the increasing use of power semiconductors and microprocessors which are very sensitive to little change of power quality and for coping positively with anticipating power quality disputes between power providers and consumers which are possible to occur by of power market being formed, the power quality problem has gained preponderance among the contemporary research areas. To serve these purposes, the integrated system has been researched and developed for power quality analysis and monitoring, which provides speedy and powerful functions by the growth of computer hardware and information technology. But the advent of fast and lower price hardware make little difference in an application on many systems. As a result, the key issues of constructing power quality monitoring system are in the management of data obtained, accurate algorithms, graphic representation and user-friendly-environment for easy and clear analysis results. So, in this paper it will be introduced that the standard of user-friendly-GUI(Graphic User Interface) and analysis graphic representation for intuitive understanding of results from power quality analysis based on consideration of several systems currently being in use.

• 대한전자공학회논문지SD
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• 제45권9호
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• pp.85-95
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• 2008

3D 그래픽 알고리즘은 특성상 방대한 양의 스트림 데이터에 대하여 복잡한 연산을 수행하여야 한다. 이러한 알고리즘을 하드웨어에서 신속하게 수행할 수 있는 버텍스 셰이더와 픽셀 세이더의 도입으로 그래픽 프로세서는 "소프트웨어 셰이더의 하드웨어화"라는 목표를 어느 정도 달성한 것처럼 보이지만, 여전히 Z-버퍼 기반이라는 특정 알고리즘의 틀에서 벗어나지 못하고 있다. 향후 그래픽 프로세서가 궁극적으로 추구하는 모델은 알고리즘에 독립적인 그리고 버텍스 셰이더와 픽셀 셰이더가 통합된 셰이더로 발전할 것이다. 본 논문에서는 프로그래머블 통합 셰이더 프로세서에서 고성능 3차원 컴퓨터 그래픽 영상을 지원하기 위한 멀티포트 레지스터 파일 모델을 설계하고 구현하였다. 설계한 멀티포트 레지스터 파일을 기능적 레벨에서 시뮬레이션을 하여 그 성능을 검증 하였으며, FPGA Virtex-4(xc4vlx200)에 직접 구현하여 하드웨어 리소스 사용율과 속도를 확인 하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.715-718
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• 2005

Mobile devices is getting to include more functions according to the demand of digital convergence. Applications based on 3D graphic calculation such as 3D games and navigation are one of the functions. 3D graphic calculation requires heavy calculation. Therefore, we need dedicated 3D graphic hardware unit with high performance. 3D graphic calculation needs a lot of complicated floating-point arithmetic operation. However, most of current mobile 3D graphics processors do not have efficient architecture for mobile devices because they are based on those for conventional computer systems. In this paper, we propose arithmetic units for special functions of lighting operation of 3D graphics. Transcendental arithmetic units are designed using approximation of logarithm function. Special function units for lighting operation such as reciprocal, square root, reciprocal of square root, and power can be obtained. The proposed arithmetic unit has lower error rate and smaller silicon area than conventional arithmetic architecture.