• Corrosion Science and Technology
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• v.20 no.5
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• pp.289-294
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• 2021

In this study, after measuring polarization characteristics of 97.3 wt% Ag, Au-Coated 97.3 wt% Ag (ACA) and 100 wt% Au wires in 1 wt% H₂SO₄ and 1 wt% HCl electrolytes at 25 ℃, corrosion rate and corrosion characteristics were comparatively analyzed. Comparing corrosion potential (E_CORR) values in sulfuric acid solution, ACA wire had more than six times higher E_CORR value than Au wire. Thus, it seems possible to use a broad applied voltage range of bonding wire for semiconductor packaging which ACA wire could be substituted for the Au wire. However, since the E_CORR value of ACA wire was three times lower than that of the Au wire in a hydrochloric acid solution, it was judged that the use range of the applied voltage and current of the bonding wire should be considered. In hydrochloric acid solution, 97.3 wt% Ag wire showed the highest corrosion rate, while ACA and Au showed similar corrosion rates. Additionally, in the case of sulfuric acid solution, all three types showed lower corrosion rates than those under the hydrochloric acid solution environment. The corrosion rate was higher in the order of 97.3 wt% Ag > ACA > 100 wt% Au wires.

• Asia-Pacific Journal of Business Venturing and Entrepreneurship
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• v.7 no.3
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• pp.17-25
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• 2012

Wire bonding process in making semiconductor needs the most precise control and Critical To Quality(CTQ). Thus, it is regarded to be the most essential step in packaging process. In this process, pure gold wire is used to connect the chip and PCB(substrate or lead frame). However, the price of gold has been skyrocketing continuously for a long period of time and is expected to further increase in the near future. This phenomenon situates us in an unfavorable condition amidst the competitive environment. To avoid this situation, many semiconductor material making companies developed new types of wires: Au.Ag wire is one material followed by many others. This study is aimed to optimize the parameter in wire bonding with the use of 6sigma and QFD(Quality Function Deployment). 6sigma process is a good means to not only solve the problem, but to increase productivity. In order to find the key factor, we focused on VOB(Voice of Business) and VOC(Voice of Customer). The main factors from VOB, VOC are called CTQ. However, there were times when these main factors were far from offering us the correct answer, thus making the situation more difficult to handle. This study shows that QFD aids in deciding which of the accurate factors to undertake. Normally QFD is used in designing and developing products. 6sigma process is held more effective when it used with QFD.

• Journal of the Korean institute of surface engineering
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• v.29 no.6
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• pp.714-719
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• 1996

For the fabrication of the circuits, contact or terminal areas are usually coated with nickel and gold. Usually, diluted palladium solution is applied to initiate electroless nickel plating on the copper circuits. However, the trace amounts of palladium remains on the resin and it causes the extraneous deposition. We confirmed that selectivity was greatly improved by the treatment with the strong reducing agents such as SBH or DMAB. Bondability was greatly influenced by the contents of phosphorus in the deposited nickel. Stabilizers in the electroless gold plating were also influenced the bonding strength. The baths containing cupferron or potassium nickel cyanide as a stabilizer showed superior bondability. The gold deposits having strong orientation with Au(220) and Au(311) showed good bond ability.

• Journal of Adhesion and Interface
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• v.25 no.2
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• pp.63-68
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• 2024

In this study, the contamination of gold(Au) wire according to the types of rinse applied for surface treatment in the wire bonding process is investigated and confirmed. For the surface treatment, rinses containing silicon(Si) or those based on organic materials are mainly employed. To identify their effects, surface treatment is conducted on Au wire using two types of rinse at a 1.0 wt% concentration, referred to as Si-including and Oil-based rinse-coated Au wire. Subsequently, a simulation experiment is performed to verify the reactivity of dust containing Si components that could occur in the semiconductor process. Through optical microscopy (OM) and scanning electron microscopy(SEM) analysis, it is observed that a larger amount of dust is adsorbed on the surface of Si-including rinse-coated Au wire compared with the Oil-based rinse-coated Au wire. This is attributed that the rinse containing Si components is relatively polar, causing polar interactions with dust, which also has polarity. Therefore, it is expected that using a rinse without Si components can reduce contamination caused by dust, thereby decreasing the defect rate in the practical wire bonding process.

• Bulletin of the Korean Chemical Society
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• v.14 no.6
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• pp.696-700
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• 1993

Gold bonding wire of 0.076 mm in diameter used in semiconductor industry, is dissoved in aqua regia. The solution is then evaporated to near dryness several times with a few drops of HCl added to prepare the final sample solution in 5% HCl. The gold matrix is separated from trace impurities by controlled potential deposition. The whole electrolysis has been carried out inside a clean bench. An optimum potential is found to be +0.25 V to give more than 99.9% Au matrix removal with better than 90 analytes remaining in the electrolyte solution. Isotope dilution calibration is employed to get the best accuracy and precision. Analytical results are presented with determination limits of the analytical method.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.327-330
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• 1998

A 2watts MMIC(Monolithic Microwave Integrated Circuits) SSPA(Solid State Power Amplifiers) for 20GHz band communication systems has been designed, manufactured and measured. The 0.15um pHEMT technologywith the gate size of 400um for single device was used for the fabrication of MMIC Power Amplifier chips. The precision MIC patterns for the peripherals like power combiner/divider and microstrip lines were realized using hard substrate for gold wire/ribbon bonding. The measured data shows that this MMIC SSPA has the linear gain of 18dB, output power of 33.42dBm(2.2Watts)at 20~21GHz.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.04a
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• pp.57-64
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• 2000

As integrated circuits become more complex, the number of I/O connections per chip grow. Conventional wire-bonding, lead-frame mounting techniques are unable to keep up. The space saved by shrinking die size is lost when the die is packaged in a huge device with hundreds of leads. The solution is bumps; gold, conductive adhesive, but most importantly solder bumps. Virtually every semiconductor manufacturer in the world is using or planning to use bump technology fur their larger and more complex devices. Several wafer-bumping processes used in the manufacture of bumped wafer. Some of the more popular techniques are evaporative, stencil or screen printing, electroplating, electrodes nickel, solder jetting, stud bumping, decal transfer, punch and die, solder injection or extrusion, tacky dot process and ball placement. This paper will discuss the process steps for bumping wafers using these techniques. Critical cleaning is a requirement for each of these processes. Key contaminants that require removal are photoresist and flux residue. Removal of these contaminants requires wet processes, which will not attack, wafer metallization or passivation. research has focused on enhanced cleaning solutions that meet this critical cleaning requirement. Process parameters defining time, temperature, solvency and impingement energy required to solvate and remove residues from bumped wafers will be presented herein.

• Journal of the Microelectronics and Packaging Society
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• v.7 no.1
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• pp.51-59
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• 2000

As integrated circuits become more complex, the number of I/O connections per chip grow. Conventional wire-bonding, lead-frame mounting techniques are unable to keep up. The space saved by shrinking die size is lost when the die is packaged in a huge device with hundreds of leads. The solution is bumps; gold, conductive adhesive, but most importantly solder bumps. Virtually every semiconductor manufacturer in the world is using or planning to use bump technology for their larger and more complex devices. Several wafer-bumping processes used in the manufacture of bumped wafer. Some of the more popular techniques are evaporative, stencil or screen printing, electroplating, electroless nickel, solder jetting, stud humping, decal transfer, punch and die, solder injection or extrusion, tacky dot process and ball placement. This paper will discuss the process steps for bumping wafers using these techniques. Critical cleaning is a requirement for each of these processes. Key contaminants that require removal are photoresist and flux residue. Removal of these contaminants requires wet processes, which will not attack, wafer metallization or passivation. Research has focused on enhanced cleaning solutions that meet this critical cleaning requirement. Process parameters defining time, temperature, solvency and impingement energy required to solvate and remove residues from bumped wafers will be presented herein.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.49 no.5
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• pp.283-288
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• 2000

In this work, small-size, high-performance simple solenoid-type RF chip inductors utilizing an Al2O3 core material were investigated. Copper (Cu) wire with $40\mum$ diameter was used as the coils and the size of the chip inductor fabricated in this work was $2.1mm\times1.5mm\times1.0mm$. The external current source was applied after bonding Cu coil leads to gold pads electro-plated on each end of backsides of a core material. High frequency characteristics of the inductance (L), quality factor (Q), and impedance (Z) of developed inductors were measured using an RF Impedance/Material Analyzer (HP4291B with HP16193A test fixture). This HP4291B was also used to obtain the equivalent circuit and its circuit parameters of the chip inductors. This HP4291B was also used to obtain the equivalent circuit and its circuit parameters of the chip inductors. The developed inductors have the self-resonant frequency (SRF) of 1.1 to 3.1 GHz and exhibit L of 22 to 150 nH. The L of the inductors decreases with increasing the SRF. The Z of the inductors has the maximum value at the SRF and the inductors have the quality factor of 70 to 97 in the frequency range of 500 MHz to 1.5 GHz.

• Journal of the Microelectronics and Packaging Society
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• v.7 no.3
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• pp.45-54
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• 2000

The effect of electropolishing far stamped leadframe on the removal of the edge burr and residual stress relief was examined. The present study showed that the electropolishing could be used for enhanced surface quality of stamped leadframes. The electropolishing was performed at the condition of 60% phosphoric acid electrolyte, 5 ampere of current and 3 cm electrode gap at $70^{\circ}C$ for 2 minutes for Alloy42 type leadframe, and $50^{\circ}C$ for 1.5 minutes for C-194 type leadframe. The FWHM values from X-ray diffraction showed that residual stress of electropolished leadframe recovered to the level of as-received raw materials and surface roughness measured by using AFM tuned out to be improved by 0.079 $\mu\textrm{m}$ and 0.014 $\mu\textrm{m}$ ($R_{rms}$) far alloy 42 and C-194 type leadframes, respectively. The plated thickness using XRF showed the improved uniformity in thickness variation by 0.4~0.5 $\mu\textrm{m}$ and grain growth, which is favorable for interface adhesion, was also observed from the bake test samples. We could certify dimensional stability of leadframe with inspection by means of 3D-topography and hardness measurements.