• Title/Summary/Keyword: Gigabit network

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A Fast IP Lookups using Dynamic Trie Compression (능동적 트라이 압축을 이용한 고속 IP 검색)

  • Oh, Seung-Hyun
    • The KIPS Transactions:PartA
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    • v.10A no.5
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    • pp.453-462
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    • 2003
  • IP address lookup of router searches and decide proper output link using destination address of IP packet that arrie into router. The IP address lookup is essential part in te development of high-speed router needed to high-speed backbone network as one of bottleneck of router performance. This paper introduces DTC data structure that can support gigabit IP address lookup by dynamic trie compression technique that just uses small memory in conventional Pentium CPU. When make a forwarding table by trie compression, the DTC can dynamically select a size of data structure with considering correlation between table's size and searching speed. Also, when compress the prefix trie, DTC makes IP address lookup on the forwarding table of a search on the high speed SRAM cache by minimizing the size of data structure reflecting the structure of the trie. In the experiment result, the DTC data structure recorded performance of maximum $12.5{\times}10^5$ LPS (lookup per second) in conventional Pentium CPU through a dynamic building of most suitable compression over variety of routing tables.

The software architecture for the internal data processing in Gigabit IP Router (기가비트 라우터 시스템에서의 내부 데이터 처리를 위한 소프트웨어 구조)

  • Lee, Wang-Bong;Chung, Young-Sik;Kim, Tae-Il;Bang, Young-Cheol
    • The KIPS Transactions:PartC
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    • v.10C no.1
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    • pp.71-76
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    • 2003
  • Internet traffic is getting tremendously heavier due to the exponential growth of the Internet users, the spread of the E-commerce and the network games. High-speed routers for fast packet forwarding are commercially available to satisfy the growing bandwidth. A high-speed router, which has the decentralized multiprocessing architecture for IP and routing functions, consists of host processors, line interfaces and switch fabrics. In this paper, we propose a software architecture tuned for high-speed non-forwarding packet manipulation. IPCMP (Inter-Processor Communication Message Protocol), which is a mechanism for IPC (Inter-Processor Communication), is also proposed and implemented as well. Proposed IPC mechanism results in faster packet-processing rate by 10% as compared to the conventional IPC mechanism using UDP/IP.

2.5 Gbps Hybrid PON link Using RSOA Based WDM-PON and a Reach Extender (RSOA기반 WDM-PON 링크와 Reach Extender를 이용한 2.5 Gbps 하이브리드 PON 링크 기술)

  • Kim, Kwang-Ok;Lee, Jie-Hyun;Lee, Sang-Soo;Jang, Youn-Seon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.36 no.6B
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    • pp.583-591
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    • 2011
  • We presents the architecture of the 2.5 Gbps hybrid PON link which can increase of the transmission distance and link capability, and split ratio by using a colorless DWDM-PON and O/E/O based reach extender into an existing G-PON link. A RSOA based DWDM-PON to apply the feeder fiber can provide a link capacity of 32 larger that of a legacy G-PON. The reach extender converts the wavelength of DWDM-PON to G-PON through GTC frame regeneration at the remote node, and can provide a burst reset signal in order to extract upstream burst signal, simultaneously. The proposed hybrid PON enable a legacy G-PON to operate over the maximum 60 km distance with a 128-way split per WDM wavelength.

A VIA-based RDMA Mechanism for High Performance PC Cluster Systems (고성능 PC 클러스터 시스템을 위한 VIA 기반 RDMA 메커니즘 구현)

  • Jung In-Hyung;Chung Sang-Hwa;Park Sejin
    • Journal of KIISE:Computer Systems and Theory
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    • v.31 no.11
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    • pp.635-642
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    • 2004
  • The traditional communication protocols such as TCP/IP are not suitable for PC cluster systems because of their high software processing overhead. To eliminate this overhead, industry leaders have defined the Virtual Interface Architecture (VIA). VIA provides two different data transfer mechanisms, a traditional Send/Receive model and the Remote Direct Memory Access (RDMA) model. RDMA is extremely efficient way to reduce software overhead because it can bypass the OS and use the network interface controller (NIC) directly for communication, also bypass the CPU on the remote host. In this paper, we have implemented VIA-based RDMA mechanism in hardware. Compared to the traditional Send/Receive model, the RDMA mechanism improves latency and bandwidth. Our RDMA mechanism can also communicate without using remote CPU cycles. Our experimental results show a minimum latency of 12.5${\mu}\textrm{s}$ and a maximum bandwidth of 95.5MB/s. As a result, our RDMA mechanism allows PC cluster systems to have a high performance communication method.

Implant Isolation Characteristics for 1.25 Gbps Monolithic Integrated Bi-Directional Optoelectronic SoC (1.25 Gbps 단일집적 양방향 광전 SoC를 위한 임플란트 절연 특성 분석)

  • Kim, Sung-Il;Kang, Kwang-Yong;Lee, Hai-Young
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.8
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    • pp.52-59
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    • 2007
  • In this paper, we analyzed and measured implant isolation characteristics for a 1.25 Gbps monolithic integrated hi-directional (M-BiDi) optoelectronic system-on-a-chip, which is a key component to constitute gigabit passive optical networks (PONs) for a fiber-to-the-home (FTTH). Also, we derived an equivalent circuit of the implant structure under various DC bias conditions. The 1.25 Gbps M-BiDi transmit-receive SoC consists of a laser diode with a monitor photodiode as a transmitter and a digital photodiode as a digital data receiver on the same InP wafer According to IEEE 802.3ah and ITU-T G.983.3 standards, a receiver sensitivity of the digital receiver has to satisfy under -24 dBm @ BER=10-12. Therefore, the electrical crosstalk levels have to maintain less than -86 dB from DC to 3 GHz. From analysed and measured results of the implant structure, the M-BiDi SoC with the implant area of 20 mm width and more than 200 mm distance between the laser diode and monitor photodiode, and between the monitor photodiode and digital photodiode, satisfies the electrical crosstalk level. These implant characteristics can be used for the design and fabrication of an optoelectronic SoC design, and expended to a mixed-mode SoC field.

Development of a Real-time OS Based Control System for Laparoscopic Surgery Robot (복강경 수술로봇을 위한 실시간 운영체제 기반 제어 시스템의 개발)

  • Song, Seung-Joon;Park, Jun-Woo;Shin, Jung-Wook;Kim, Yun-Ho;Lee, Duk-Hee;Jo, Yung-Ho;Choi, Jae-Seoon;Sun, Kyung
    • Journal of Biomedical Engineering Research
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    • v.29 no.1
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    • pp.32-39
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    • 2008
  • This paper reports on a realtime OS based master-slave configuration robot control system for laparoscopic surgery robot which enables telesurgery and overcomes shortcomings with conventional laparoscopic surgery. Surgery robot system requires control system that can process large volume information such as medical image data and video signal from endoscope in real-time manner, as well as precisely control the robot with high reliability. To meet the complex requirements, the use of high-level real-time OS (Operating System) in surgery robot controller is a must, which is as common as in many of modem robot controllers that adopt real-time OS as a base system software on which specific functional modules are implemened for more reliable and stable system. The control system consists of joint controllers, host controllers, and user interface units. The robot features a compact slave robot with 5 DOF (Degree-Of-Freedom) expanding the workspace of each tool and increasing the number of tools operating simultaneously. Each master, slave and Gill (Graphical User Interface) host runs a dedicated RTOS (Real-time OS), RTLinux-Pro (FSMLabs Inc., U.S.A.) on which functional modules such as motion control, communication, video signal integration and etc, are implemented, and all the hosts are in a gigabit Ethernet network for inter-host communication. Each master and slave controller set has a dedicated CAN (Controller Area Network) channel for control and monitoring signal communication with the joint controllers. Total 4 pairs of the master/slave manipulators as current are controlled by one host controller. The system showed satisfactory performance in both position control precision and master-slave motion synchronization in both bench test and animal experiment, and is now under further development for better safety and control fidelity for clinically applicable prototype.