• IEMEK Journal of Embedded Systems and Applications
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• v.2 no.4
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• pp.251-259
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• 2007

AUTOSAR is a partnership of automotive manufacturers and suppliers working together to develop and establish a de-facto open industry standard for automotive software architectures. In the AUTOSAR architecture, the runtime environment is at in the heart of the AUTOSAR architecture to provides the infrastructure services that enable communication between software components and between software components and basic software components. The RTE generator is an automated generation tool for AUTOSAR specification based RTE according to the ECU configuration. It generates communication API function for the software components and the basic software components like OS and COM of the application. The availability and the accuracy of the RTE generator are important for the automobile software which is based on AUTOSAR architecture, this paper proposes an architectural design of the RTE generator for auto-generation of the AUTOSAR based RTE.

• Proceedings of the Korea Multimedia Society Conference
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• 2003.05b
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• pp.14-18
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• 2003

This paper presents the pipeline architecture for the low and column address generator of 2D DCT/IDCT(Discrete Cosine Transform/Inverse Discrete Cosine Transform). For the real time process of image data, it is required that high speed operation and small size hardware In the proposed architecture, the area of hardware is reduced by using the DA(distributed arithmetic) method and applying the concepts of pipeline on the parallel architecture. As a results, the designed pipeline of the low and column address generator for 2D DCT/IDCT architecture is implemented with an efficiency and high speed compared as the non-pipeline architecture. And the operation speed is improved about 50％ up. The design for the proposed pipeline architecture of DCT/IDCT is coded using VHDL.

• Current Optics and Photonics
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• v.2 no.5
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• pp.400-406
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• 2018

The Semiconductor Optical Amplifier (SOA)-based Mach-Zehnder interferometer is a major contributor in all-optical digital processing and optical computation. Optical tree architecture provides one of the new, alternative schemes for integrated all-optical arithmetic and logical operations. In this paper, we propose an all-optical 3-bit integrated parity generator and checker using SOA-MZI-based optical tree architecture. The proposed scheme, able to process input signals at a desired operating wavelength, has been characterized using RZ-modulated signals at 10 Gbps. The maximum extinction ratios achieved at the output of the parity generator and checker are 10 dB and 8 dB respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.3
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• pp.613-619
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• 2017

In this paper, DF(Dual Fuel) Generator modeling, which uses both conventional diesel fuel and LNG fuel, has been performed and monitoring system has been developed based on MATLAB/SIMULINK for the development of PMS(Power Management System) HILS(Hardware In the Loop Simulation). The principal components modeling of DF Generator are DF engine which provides the mechanical power and synchronous generator which convert the mechanical power into electrical power. Submodels, such as throttle body, intake manifold, torque generation and mass of LNG and diesel Quantity are used to perform DF engine. Also, governor is used for load sharing between paralleled DF generators to share a total load that exceeds the capacity of a single generator. To verify modeling of DF Generator designated ship lumped load Simulation is carried out. A validity of DF Generator has been verified by comparison between simulation results and estimated result from the designated lumped load.

• 한국태양에너지학회:학술대회논문집
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• 2008.11a
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• pp.126-131
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• 2008

The large buildings in Korea usually use the generators to control the peak load of electronic consumption during the summer. It is necessary that these generators emit carbon dioxide, since they use gas or gasoline for their fuel. This study is to analyze the data of electronic consumption and operation of the generators at COEX, one of the representative complex building clusters in Korea, and to compare to the amount of carbon dioxide emitted per 1kWh from the domestic power plant by analogizing the frequency of using the generator during the summer and the amount of fuel consumption by the capacity of the generator and estimating the amount of carbon dioxide emitted from the generator.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.6C
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• pp.619-625
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• 2009

This paper proposes a parallel architecture of a Parity Checksum Generator adopted for packet synchronization and error detection in the ITU-T Recommendation J.83 Annex B. The proposed parallel processing architecture removes a performance bottleneck occurred in a conventional serial processing architecture, leading to significant decrease in processing time for generating a Parity Checksum. The implementation results show that the proposed parallel processing architecture reduces the processing time by 83.1% at the expense of 16% area increase.

• Journal of the Korea Society of Computer and Information
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• v.27 no.7
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• pp.27-33
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• 2022

In this paper, we propose a novel generator architecture for multi-domain style transfer method not an image to image translation, as a method of generating a styled image by transfering a style to the content image. A latent vector and Gaussian noises are added to the generator of GAN so that a high quality image is generated while considering the characteristics of various data distributions for each domain and preserving the features of the content data. With the generator architecture of the proposed GAN, networks are configured and presented so that the content image can learn the styles for each domain well, and it is applied to the domain composed of images of the four seasons to show the high resolution style transfer results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.11
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• pp.2978-2990
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• 1996

With the advent of multimedia era, there are ever increasing interest in computer music and sound syntheis. An FM type sound synthesizing method makes possible the syntheis ofvarious sounds ofmusical instruments with a relatively simple hardware architecture. Therefore, in this paper, we designed a hardware architecture for real-time sound synthesizer and its logic gates. In this paper, we designed a basic sound generator for implementation of real-time logic gates, analzed characteristics of sounds synthesized in this architecture and extracted parameters of FM sounds of musical instruments by using the Csound software. The major bolkcs to build the hardware are a phase-generator, a singe-function-generator, an envelope-generator and a multiplier-part. Finally, logic circuits are designed and verified in VHDL and logic gates by 1.0um standard cell library, which will be easily implementable by the form of ASIC.

• Journal of the Institute of Convergence Signal Processing
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• v.3 no.4
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• pp.23-28
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• 2002

In this paper, we have proposed the hardware architecture which implements the algorithm for retaining the connectivity which prevents the disconnection in the gray-scale image thinning. To extract the skeleton from the image in a real time, it is necessary to examine the connectivity of the skeleton in a real time. The proposed architecture finds the connectivity number in the 4-clock period. The architecture consists of three blocks, PS(Parallel to Serial) Converter and Stare Generator and Ridge Checker. The PS Converter changes the 3$\times$3 gray level image to four sets of image pixels. The State Generator examines the connectivity of the central pixel by searching the data from the PS Converter. The Ridge Checker determines whether the central pixel is on the skeleton or not. The proposed architecture finds the connectivity of the central pixel in a 3$\times$3 gray level image in the 4-clocks. The total circuits are verified by the design tools and operate correctly.

• Journal of the Society of Naval Architects of Korea
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• v.54 no.6
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• pp.461-469
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• 2017

A segment of the wave board has been expressed as a submerged line segment in the two dimensional wave flume. The lower end of the line segment could be extended to the bottom of the wave flume and the other opposite upper end of the board could be extended to the free surface. It is assumed that the motion of the wave board could be defined by the sinusoidal motion in horizontal direction on either end of the wave board. When the amplitude of sinusoidal motion of the wave board on lower and upper end are equal, the wave board motion could express the horizontally oscillating submerged segment of piston type wave generator. The submerged segment of flap type wave generator also could be expressed by taking the motion amplitude differently for the either end of the board. The pivot point of the segment motion could play a role of hinge point of the flap type wave generator. Simplified analytic solution of oscillating submerged wave board segment in water of finite depth has been derived through the first order perturbation method at two dimensional domain. The case study of the analytic solution has been carried out and it is found out that the solution could be utilized for the design of wave generator with arbitrary shape by linear superposition.