• Title/Summary/Keyword: Generating Codes

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MINIMAL QUADRATIC RESIDUE CYCLIC CODES OF LENGTH $2^{n}$

  • BATRA SUDHIR;ARORA S. K.
    • Journal of applied mathematics & informatics
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    • v.18 no.1_2
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    • pp.25-43
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    • 2005
  • Let F be a finite field of prime power order q(odd) and the multiplicative order of q modulo $2^{n}\;(n>1)\;be\; {\phi}(2^{n})/2$. If n > 3, then q is odd number(prime or prime power) of the form $8m{\pm}3$. If q = 8m - 3, then the ring $R_{2^n} = F[x]/ < x^{2^n}-1 >$ has 2n primitive idempotents. The explicit expressions for these primitive idempotents are obtained and the minimal QR cyclic codes of length $2^{n}$ generated by these idempotents are completely described. If q = 8m + 3 then the expressions for the 2n - 1 primitive idempotents of $R_{2^n}$ are obtained. The generating polynomials and the upper bounds of the minimum distance of minimal QR cyclic codes generated by these 2n-1 idempotents are also obtained. The case n = 2,3 is dealt separately.

ON THE IDEMPOTENTS OF CYCLIC CODES OVER 𝔽2t

  • Sunghyu, Han
    • Korean Journal of Mathematics
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    • v.30 no.4
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    • pp.653-663
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    • 2022
  • We study cyclic codes of length n over 𝔽2t. Cyclic codes can be viewed as ideals in 𝓡n = 𝔽2t [x]/(xn − 1). It is known that there is a unique generating idempotent for each ideal. Let e(x) ∈ 𝓡n. If t = 1 or t = 2, then there is a necessary and sufficient condition that e(x) is an idempotent. But there is no known similar result for t ≥ 3. In this paper we give an answer for this problem.

m-ADIC RESIDUE CODES OVER Fq[v]/(v2 - v) AND DNA CODES

  • Kuruz, Ferhat;Oztas, Elif Segah;Siap, Irfan
    • Bulletin of the Korean Mathematical Society
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    • v.55 no.3
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    • pp.921-935
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    • 2018
  • In this study we determine the structure of m-adic residue codes over the non-chain ring $F_q[v]/(v^2-v)$ and present some promising examples of such codes that have optimal parameters with respect to Griesmer Bound. Further, we show that the generators of m-adic residue codes serve as a natural and suitable application for generating reversible DNA codes via a special automorphism and sets over $F_{4^{2k}}[v]/(v^2-v)$.

Introduction to the NREL Design Codes for System Performance Test of Wind Turbines - Part I : Preprocessor (풍력터빈 시스템 성능평가를 위한 NREL 프로그램군에 관한 소개 - 전처리기를 중심으로)

  • Bang, Je-Sung;Rim, Chae Whan;Chung, Tae Young
    • 한국신재생에너지학회:학술대회논문집
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    • 2011.11a
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    • pp.41.2-41.2
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    • 2011
  • NREL NWTC Deside codes are analyzed and introduced to develop the system performance simulation program for wind turbine generator systems. In this paper, The AirfoilPrep generating the airfoil data, the IECWind generating hub-height wind data with extreme condition following IEC 61400-1, the TurbSim generating stochastic full-field turbulent wind data, the PreComp calculating structural and dynamic properties of composite blade and the BModes making mode shapes of blade and tower are explained respectively.

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Design and Investigation of new composite code (새로운 주기 확장된 코드에 관한 연구)

  • 임지형;김운경;이경록
    • Proceedings of the IEEK Conference
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    • 2000.11a
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    • pp.61-64
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    • 2000
  • There are many methods of generating PN sequences. In this paper, we propose and examine a new class of composite shift register to generate PN sequences. The new composite generator, in comparison with the original LFSR which generates PN codes of period 2$^n$-1, when coupled with codes of period k, generates PN codes with (longer) period LCM(2$^n$-1,k).

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Implementation of systematic LT codes using VHDL (VHDL을 이용한 시스터메틱 LT 부호의 구현)

  • Zhang, Meixiang;Kim, Sooyoung;Chang, Jin Yeong;Kim, Won-Yong
    • Journal of Satellite, Information and Communications
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    • v.9 no.2
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    • pp.45-51
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    • 2014
  • Luby transform (LT) codes are a class of ratelss codes, and they have capability of generating infinite length of parities with a given information length. These rateless codes can be effectively utilized to provide broadcasting and multicasting services where each user is in a different channel condition. For this reason, there have been a number of researches on the application of rateless codes for satellite systems. In this paper, by considering the current research status on rateless codes, we present VHLD implementation results of LT codes, for future hardware implementation for satellite systems. The results demonstrated in this paper can be utilized as a basic information on efficient utilization of rateless codes in the future satellite systems.

Designing a Classification System for Minhwa DB (민화 DB를 위한 분류체계 설계)

  • Choi, Eunjin;Lee, Young-Suk
    • Journal of Korea Multimedia Society
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    • v.25 no.1
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    • pp.135-143
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    • 2022
  • In order to convert Korean folk paintings called Minhwa, a part of traditional Korean heritage, into DBs, it is necessary to design a classification system suitable for the characteristics of folk paintings. A classification system and the generating of unique codes are required to classify and save them. To realize this, a basic classification system was created by listing objects depicted in folk paintings, and keywords were extracted by reclassifying them for each object. In order to assign a unique code to each piece, we organize the English names of each Minhwa since the English names of the folk painting contain the names of objects. The code name is extracted by applying the order of nouns and consonant priority rules in English names and attaching five Arabic numerals. These codes are later assigned to each image file stored in the database and are input together with the keyword. The Minhwa DB constructed in this way enables storage and search centered on objects and keywords and the intuitive inferring of the type of object from the code name.

Profile Guided Selection of ARM and Thumb Instructions at Function Level (함수 수준에서 프로파일 정보를 이용한 ARM과 Thumb 명령어의 선택)

  • Soh Changho;Han Taisook
    • Journal of KIISE:Software and Applications
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    • v.32 no.3
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    • pp.227-235
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    • 2005
  • In the embedded system domain, both memory requirement and energy consumption are great concerns. To save memory and energy, the 32 bit ARM processor supports the 16 bit Thumb instruction set. For a given program, the Thumb code is typically smaller than the ARM code. However, the limitations of the Thumb instruction set can often lead to generation of poorer quality code. To generate codes with smaller size but a little slower execution speed, Krishnaswarmy suggests a profiling guided selection algorithm at module level for generating mixed ARM and Thumb codes for application programs. The resulting codes of the algorithm give significant code size reductions with a little loss in performance. When the instruction set is selected at module level, some functions, which should be compiled in Thumb mode to reduce code size, are compiled to ARM code. It means we have additional code size reduction chance. In this paper, we propose a profile guided selection algorithm at function level for generating mixed ARM and Thumb codes for application programs so that the resulting codes give additional code size reductions without loss in performance compared to the module level algorithm. We can reduce 2.7% code size additionally with no performance penalty

Comparison of EXIT chart generation for LDPC and turbo codes (시뮬레이션 기법을 이용한 LDPC 부호와 터보부호에 대한 EXIT 차트 생성 비교)

  • Nyamukondiwa, Ramson Munyaradzi;Kim, Sooyoung
    • Journal of Satellite, Information and Communications
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    • v.10 no.3
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    • pp.73-77
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    • 2015
  • In this paper, we present two simulation methods to investigate the effect of excluding bit errors on generating the extrinsic information transfer (EXIT) chart for low density parity check (LDPC) and turbo codes. We utilized the simulation methods including and excluding bit errors to generate EXIT chart which was originally proposed for turbo codes. The generated EXIT charts for LDPC and turbo codes shows that the presented methods appropriately demonstrates the performance behaviours of iterative decoding for LDPC and turbo codes. Analysis on the simulation results demonstrates that the EXIT chart excluding the bit errors shows only a small part of the curves where the amount of information is too large.

HTSC and FH HTSC: XOR-based Codes to Reduce Access Latency in Distributed Storage Systems

  • Shuai, Qiqi;Li, Victor O.K.
    • Journal of Communications and Networks
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    • v.17 no.6
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    • pp.582-591
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    • 2015
  • A massive distributed storage system is the foundation for big data operations. Access latency performance is a key metric in distributed storage systems since it greatly impacts user experience while existing codes mainly focus on improving performance such as storage overhead and repair cost. By generating parity nodes from parity nodes, in this paper we design new XOR-based erasure codes hierarchical tree structure code (HTSC) and high failure tolerant HTSC (FH HTSC) to reduce access latency in distributed storage systems. By comparing with other popular and representative codes, we show that, under the same repair cost, HTSC and FH HTSC codes can reduce access latency while maintaining favorable performance in other metrics. In particular, under the same repair cost, FH HTSC can achieve lower access latency, higher or equal failure tolerance and lower computation cost compared with the representative codes while enjoying similar storage overhead. Accordingly, FH HTSC is a superior choice for applications requiring low access latency and outstanding failure tolerance capability at the same time.