• Proceeding of EDISON Challenge
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• 2014.03a
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• pp.457-458
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• 2014

In this paper, quantum mechanical simulations of the double-gate ultra-thin body (DG-UTB) MOSFETs are performed according to the International Technology Roadmap of Semiconductors (ITRS) specifications planned for 2020, to devise the way for on-current ($I_{on}$) improvement. We have employed non-equilibrium Green's function (NEGF) approach and solved the self-consistent equations based on the parabolic effective mass theory [1]. Our study shows that the [100]/<001> Ge and GaSb channel devices have higher $I_{on}$ than Si channel devices under the body thickness ($T_{bd}$) <5nm condition.

• Journal of the Korean Ceramic Society
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• v.37 no.6
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• pp.524-529
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• 2000

Silica slab wavegudie was fabricated on Si substrates by FHD for planar optical passive devices. The slab waveguide consists of lower clad and core layers, where core layer index is controlled by GeO2 addition. Doping of GeO2 in silica is difficult because of the low deposition density due to nonspherical particle generation in FHD process. Silica core particles deposited at various conditions such as flame temperature and substrate scanning were analyzed by SEM and TEM. As the flame temperature increased, the surface roughness of the core layer was decreased up to 3.6 nm after consolidation. Index difference and thickness of core of slab waveguide were 0.3%, 8$\mu\textrm{m}$ respectively. Measured optical loss at TE mode was <0.04 dB/cm at 1.3$\mu\textrm{m}$ and <0.06 dB/cm at 1.55$\mu\textrm{m}$.

• Proceedings of the Korean Powder Metallurgy Institute Conference
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• 2006.09a
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• pp.79-80
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• 2006

From a viewpoint of heat stress at high temperatures and contact thermal resistance, it is confirmed that the optimal structure is the skeleton structure using Cu substrate on the cooling side, which has excellent heat conductivity and the optimal installation method is to adopt a carbon sheet and a mica sheet to the high temperature side, where Si grease is applied to the low temperature side, under pressurized condition. The power of the developed modules indicated 0.5W in an $FeSi_2$ module and 3.8 W with a SiGe module at 823K, respectively.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.130-130
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• 2011

최근 반도체 메모리 산업의 발전과 동시에 발생되는 문제들을 극복하기 위한 새로운 기술들이 요구되고 있다. DRAM (dynamic random access memory) 의 경우, 소자의 크기가 수십 나노미터 영역으로 줄어들면서, 단채널 효과에 의한 누설전류와 소비전력의 증가 등이 문제가 되고 있다. 하나의 캐패시터와 하나의 트랜지스터로 구성된 기존의 DRAM은, 소자의 집적화가 진행 되어 가면서 정보저장 능력이 감소하는 것을 개선하기 위해, 복잡한 구조의 캐패시터 영역을 요구한다. 이에 반해 하나의 트랜지스터로 구성되어 있는 1T-DRAM의 경우, 캐패시터 영역이 없는 구조적인 이점과, SOI (silicon-on-insulator) 구조의 기판을 사용함으로써 뛰어난 전기적 절연 특성과 기생 정전용량의 감소, 그리고 기존 CMOS (complementary metal oxide semiconductor) 공정과의 호환성이 장점이다. 또한 새로운 물질 혹은 구조를 적용하여, 개선된 전기적 특성을 통해 1T-DRAM의 메모리 특성을 향상 시킬 수 있다. 본 연구에서는, SOI와 SGOI (silicon-germanium-on-insulator) 및 sSOI (strained-si-on-insulator) 기판을 사용한 MOSFET을 통해, strain 효과에 의한 전기적 특성 및 메모리 특성을 평가 하였다. 그 결과 strained-Si층과 relaxed-SiGe층간의 tensile strain에 의한 캐리어 이동도의 증가를 통해, 개선된 전기적 특성 및 메모리 특성을 확인하였다. 또한 채널층의 결함이 적은 sSOI 기판을 사용한 1T-DRAM에서 가장 뛰어난 특성을 보였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.346-346
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• 2010

A capacitorless one transistor dynamic random access memory (1T-DRAM) on silicon-germanium-on-insulator substrate was investigated. SGOI technology can make high effective mobility because of lattice mismatch between the Si channel and the SiGe buffer layer. To evaluate memory characteristics of 1T-DRAM, the floating body effect is generated by impact ionization (II) and gate induced drain leakage (GIDL) current. Compared with use of impact ionization current, the use of GIDL current leads to low power consumption and larger sense margin.

• Proceedings of the Korean Vacuum Society Conference
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• 1999.07a
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• pp.65-65
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• 1999

Dry etching technique provides more easy controllability on the etch profile such as anisotropic etching than wet etching process and the results of lots of researches on the characterization of various plasmas or ion beams for semiconductor etching have been reported. Chlorine-based plasmas or chlorine ion beam have been often used to etch several semiconductor materials, in particular Si-based materials. We have studied the effect of He flow rate on the Si and SiO2 dry etching using chlorine-based plasma. Experiments were performed using reactive ion etching system. RF power was 300W. Cl2 gas flow rate was fixed at 58.6 sccm, and the He flow rate was varied from 0 to 120 sccm. Fig. 1 presents the etch depth of si layer versus the etching time at various He flow rate. In case of low He flow rate, the etch rate was measured to be negligible for both Si and SiO2. As the He flow increases over 30% of the total inlet gas flow, the plasma state becomes stable and the etch rate starts to increase. In high Ge flow rate (over 60%), the relation between the etch depth and the time was observed to be nearly linear. Fig. 2 presents the variation of the etch rate depending on the He flow rate. The etch rate increases linearly with He flow rate. The results of this preliminary study show that Cl2/He mixture plasma is good candidate for the controllable si dry etching.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.4
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• pp.295-301
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• 2008

Recently, the demand on mm-wave (millimeter-wave) applications has increased dramatically. While circuits operating in the mm-wave frequency band have been traditionally implemented in III-V or SiGe technologies, recent advances in Si MOSFET operation speed enabled mm-wave circuits realized in a Si CMOS technology. In this work, a 58 GHz CMOS LC cross-coupled VCO (Voltage Controlled Oscillator) was fabricated in a $0.13-{\mu}m$ Si RF CMOS technology. In the course of the circuit design, active device models were modified for improved accuracy in the mm-wave range and EM (electromagnetic) simulation was heavily employed for passive device performance predicttion and interconnection parasitic extraction. The measured operating frequency ranged from 56.5 to 58.5 GHz with a tuning voltage swept from 0 to 2.3 V. The minimum phase noise of -96 dBc/Hz at 5 MHz offset was achieved. The output power varied around -20 dBm over the measured tuning range. The circuit drew current (including buffer current) of 10 mA from 1.5 V supply voltage. The FOM (Figure-Of-Merit) was estimated to be -165.5 dBc/Hz.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.11 no.1
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• pp.20-26
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• 2001

Titanium boride ($\textrn{TiB}_{x}$) films were deposited on (100) silicon substrates at the substrate temperature of $500^{\circ}C$ by means of the co-evaporation of titanium and boron evaporants during deposition. The co-evaporation method makes it possible to deposit the non-stoichiometric films with different boron-to-titanium ratio($0{\le}B/Ti \le 2.5$). The resistivity increases linearly as the boron-to-titanium ratio in the as-deposited films is increased. The surface roughness of $\textrn{TiB}_{x}$ films is changed as a function of the boron-to-titanium ratio. The XRD spectrum for pure titanium film shows a highly (002) preferred orientation. For B/Ti=0.59 ratio only a single TiB phase that shows a (111) preferred orientation is observed. However, the $\textrn{TiB}_{x}$ phase with the hexagonal structure of the $AlB_2$(C32) type appears as the boron concentration increase, and only a single $\textrn{TiB}_{x}$ phase is observed for $B/Ti \ge 2.0$ ratio. The $\textrn{TiB}_{x}$/Si samples reveal a tensile stress (3~$20{\times}^9$dyn/$\textrm{cm}^2$) in the overall composition of the films, although the magnitude of the residual stresses is depended on the nominal B/Ti ratio.

• Proceedings of the Korean Vacuum Society Conference
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• 2002.06a
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• pp.162-162
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• 2002

• Proceedings of the Korean Vacuum Society Conference
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• 2007.08a
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• pp.299-299
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• 2007