• Korean Institute of Interior Design Journal
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• v.20 no.3
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• pp.190-197
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• 2011

The purpose of this study is to examine the characteristics of space design appearing in facade and interior composition factors of buildings in the colonial period in Indonesia. Research method is a field study, and subjects of the study is 14 buildings built in the colonial period located in Jakarta. The research result is as follows. First, Facade is divided into C type (colonial style), CT type (colonial style + traditional style), CA type (colonial style + art deco style), and CTA type (colonial style + traditional style + art deco style). Among them, CT type which shows both a colonial style and traditional style accounts for the most. As for Java traditional style mainly shows Joglo roof style and bratticing decoration on top of gates, and the colonial style presents both an Amsterdam canal housing style such as narrow Facade and unusual Gable, and a classical style such as pediment, entablature, and columns. Second, interior space is divided into C type (colonial style), CT type (colonial style + Indonesian traditional style), A type (art deco style), and CA type (colonial style + art deco style). Among them, CT type was also accounted for the most. Selected traditional style is a shape of bratticing decoration on top of gates and a shape of tenon of Joglo housing structure. Colonial style showed classical style such as exposed crossbeams, columns, and pilasters, and as for unique decoration, there are Ancona decoration and Delft tile decoration. On one hand, art deco style used typical art deco factors such as contrast of various materials and complementary color or golden color use as well as zigzag or vertical lines and geometric ornament by combining with colonial style or traditional style. It is expected that such research result will be a practical reference data when Korean construction companies or interior design companies advance Indonesia.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.5
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• pp.48-55
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• 2000

Recently due to rapid improvement of integrated circuit design environment, size of IC design is to become large to possible design System on Chip(SoC) that one chip with multi function enclosed. Also cause to this rapid change, consumption market is require to spend smallest time for new product development. In this paper to propose a methodology can design a large size IC for save time and applied to design of MPEG Layer 2 decoder to can use audio receiver in digital broadcast system. The digital broadcast audio decoder in this paper is pointed to save hardware size as optimizing algorithm. MPEG Layer 2 decoder algorithm is include MAC to can have an effect on hardware size. So coefficients are using sign digit expression. It is for hardware optimization. If using this method can design MAC without multiplier. The designed audio decoder is using 14,000 gates hardware size and save 22% (4000 gates) hardware usage than using multiplier. Also can design MPEG Layer 2 decoder usable digital broadcast receiver for short time.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.12
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• pp.88-93
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• 2016

This paper presents a method of constructing the highly performance switching circuit(HPSC) over finite fields. The proposed method is as following. First of all, we extract the input/output relationship of linear characteristics for the given digital switching functions, Next, we convert the input/output relationship to Directed Cyclic Graph using basic gates adder and coefficient multiplier that are defined by mathematical properties in finite fields. Also, we propose the new factorization method for matrix characteristics equation that represent the relationship of the input/output characteristics. The proposed method have properties of generalization and regularity. Also, the proposed method is possible to any prime number multiplication expression.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.12
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• pp.2201-2206
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• 2008

This paper presents a method of constructing the Linear Digital Switching Function(LDSF) over finite fields. The proposed method is as following. First of all, we extract the input/output relationship of linear characteristics for the given digital switching functions, Next, we convert the input/output relationship to Directed Cyclic Graph(DCG) using basic gates adder and coefficient multiplier that are defined by mathematical properties in finite fields. Also, we propose the new factorization method for matrix characteristics equation that represent the relationship of the input/output characteristics. The proposed method have properties of generalization and regularity. Also, the proposed method is possible to any prime number multiplication expression.

• Journal of KIISE:Computing Practices and Letters
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• v.8 no.1
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• pp.88-95
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• 2002

In recent years, the security of hardware and software systems is one of the most essential factor of our safe network community. As elliptic Curve Cryptosystems proposed by N. Koblitz and V. Miller independently in 1985, require fewer bits for the same security as the existing cryptosystems, for example RSA, there is a net reduction in cost size, and time. In this thesis, we propose an efficient hardware architecture of underlying field arithmetic processor for Elliptic Curve Cryptosystems, and a very useful method for implementing the architecture, especially multiplicative inverse operator over GF$GF (2^m)$ onto FPGA and futhermore VLSI, where the method is based on optimized unit operation components. We optimize the arithmetic processor for speed so that it has a resonable number of gates to implement. The proposed architecture could be applied to any finite field $F_{2m}$. According to the simulation result, though the number of gates are increased by a factor of 8.8, the multiplication speed We optimize the arithmetic processor for speed so that it has a resonable number of gates to implement. The proposed architecture could be applied to any finite field $F_{2m}$. According to the simulation result, though the number of gates are increased by a factor of 8.8, the multiplication speed and inversion speed has been improved 150 times, 480 times respectively compared with the thesis presented by Sarwono Sutikno et al. [7]. The designed underlying arithmetic processor can be also applied for implementing other crypto-processor and various finite field applications.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.473-478
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• 2003

To detect motions of bodies, we have discussed them with two viewpoints; one is a detection algorithm, and another is the hardware implementation. The former is to find small terms expansions for sine/cosine functions. We researched Maclaurin and optimum expansions, and moreover to reduce hardware amounts, revised the expansions. The expansions don't include divide calculations, and the error is within 0.01%. As for the former problem, there is another approach also; that is the cordic method. The method is based on the rotation of a vector on the complex plain. It is simple iterations and don't require large logic. We examined the precision and convergence of the method on C-simulations, and implemented on HDL. The later problem is to make FPGA within small gates. We considered approaches to eliminate a divider and to reduce the bit number of arithmetic. We researched Newton-Raphson's method to get reciprocal numbers. The higher-order expression shows rapid convergence and doesn't be affected by the initial guess. It is an excellent algorithm. Using them, we wish to design a detector, and are developing it on a FPGA.

• Transactions of Materials Processing
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• v.12 no.1
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• pp.34-42
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• 2003

This paper presents a rigid-plastic finite element method to handle the frictional contact problem between two deformable bodies experiencing large deformation. The variational formulation combined with incremental quasi-static model is employed for treating the contact boundary condition. The frictional behavior of the model obeys Coulomb's law of friction. The proposed contact algorithms are classified into two categories, one for searching contacting nodes and the other for calculating contact forces at the contact surface. A slave node and master contact segment are defined using the geometric condition of finite elements on the contact interface. The penalty parameter is used to limit the penetration between contacting bodies, and the finite elements are coupled with contact boundary elements.us gates and cavity thicknesses. Through this study we have observed that the jetting is related to the die swell of material. This means that the jotting is strongly affected by the elastic flow property rather than the viscous flow property in viscoelastic characteristics of molten polymer. Different resins have different elastic properties, and elastic flow behavior depends on the shear rate of flow, i.e. injection speed. Large die swell would eliminate jetting however, the retardation of die swell would stimulate jetting. In the point of mole design, reducing the thickness ratio of cavity to gate can reduce or eliminate jetting regardless of amount of elasticity of polymer melt.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.443-450
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• 2013

This paper propose a new ROM data encoding method that takes into account of a sequential access pattern to reduce the power consumption in ROMs used in applications such as FIR filters that access the ROM sequentially. In the proposed encoding method, the number of 1's, of which the increment leads to the increase of the power consumption, is reduced by applying an exclusive-or (XOR) operation to a bit pair composed of two consecutive bits in a bit line. The encoded data can be decoded by using XOR gates and D flip-flops, which are usually used in digital systems for synchronization and glitch suppression. By applying the proposed encoding method to coefficient ROMs of FIR filters designed by using various design methods, we can achieve average reduction of 43.7% over the unencoded original data in the power consumption, which is larger reduction than those achieved by previous methods.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.67 no.5
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• pp.680-687
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• 2018

Because of its predictability of the energy cycle and huge scale power output, the ocean energy from tidal power utilization has always received attention as a great energy source, even though its development cost, including the embankment construction, is so much higher than that of any other energy source. Nevertheless, nowadays many projects are being planned on account of institutional support from the government and the recent advance of construction technology. In Korea, the new industry field operating and managing the tidal power plant has already opened. But we are facing a number of problems for optimal operation of tidal power plant that are a lack of operation experience and a skill of professional management and others. This paper suggests a novel way to determine the starting head of power generation by generating power comparison method For this new method, the paper discusses many factors including changing the volume of the basin, the number of operating turbines and gates and forecasting the tidal amplitude and the characteristic curve of turbine and gate. Finally we verified that it can increase about 2% an annual power generation compared with the conventional method using the original operational function made in the plant design process.

• Journal of architectural history
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• v.20 no.5
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• pp.47-61
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• 2011

This study examined the background and change of building Yeongam eupseong and characteristics and construction method of its spatial structure. The results of this study can be summarized as follows. First, Yeongam eupseong was built for the same purpose of national border defense against the invasion of Japanese army as other Eupseongs were built and it was found first in the literature in the era of King Munjong of Joseon Dynasty with the scale of three gates and 4,369 cheok of castle wall. Such a scale was continued and in particular, according to flat structure, road network and gate position shown in the map, the form and road system of Yeongam eupseong before the 19th century were mostly identical with the current ones. Second, castle wall was built over foundation by using talcum after leveling the foundation soil and castle wall can be divided into outer wall, filling part and inner wall from the section. Outer wall was constructed by inserting and layering pebbles with big irregular stone, filling part was made with talcum and riprap and inner wall with soil in several layers by keeping gradient. This building method showed common features in inserting and layering pebbles for outer wall, use of protruded base and section form compared to Jeollado Eupseong.