• KEPCO Journal on Electric Power and Energy
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• v.3 no.2
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• pp.141-146
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• 2017

In this work, a simulation study on net 500 MW class of Poly-Generation was conducted for the retrofit of an aged natural gas combined cycle. An entrained gasifier which has a capacity of maximum $260,000Nm^3/h$, 50 MW class of a Polymer Electrolyte Membrane Fuel Cell, and H-class Gas Turbine were selected as key processes. After unit design for those employed processes was set up and combined, the simulation was carried out with Gate-Cycle software (Ver. 6.0) for two cases. The selected cases are a retrofit type (Poly-Gen 1) and a new type (Poly-Gen 2). It was found that the efficiency of the retrofit case is 2.7% lower than that of the new case.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.112-115
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• 2008

In this paper, we propose H.264 High Profile Encoder Intra Prediction module. This designed module can be operated in 306 cycle for one-macroblock. To verify the Encoder architecture, we developed the reference C from JM 13.2 and verified the our developed hardware using test vector generated by reference C. We adopt plan removal and SAD calculation to reduce the Hardware cost and cycle. The designed circuit can be operated in 133MHz clock system, and has 250K gate counts using TSMC 0.18um process including SRAM memory.

• International conference on construction engineering and project management
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• 2022.06a
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• pp.975-983
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• 2022

This paper presents an innovative way of integrating scheduling and project controls with the environmental impact of a construction project to track, monitor, and manage environmental emissions at the activity level. As a starting point, scheduling and project controls help monitor the status of a project to provide an assessment of the duration and sequence of activities. Additionally, project schedules can also reflect resource allocation and costs associated with various phases of a construction project. Owners, contractors and construction managers closely monitor tasks or activities on the critical path(s) and/or longest path(s) calculated through network based scheduling techniques. However, existing industry practices do not take into account environmental impact associated with each activity during the life cycle of a project. Although the environmental impact of a project may be tracked in various ways, that tracking is not tied to the project schedule and, as such, generally is not updated when schedules are revised. In this research, a Cradle to Gate approach is used to estimate environmental emissions associated with each activity of a sample project schedule. The research group has also investigated the potential determination of scenarios of lowest environmental emissions, just as project managers currently determine scenarios with lowest cost or time. This methodology can be scaled up for future work to develop a library of unit emissions associated with commonly used construction materials and equipment. This will be helpful for project owners, contractors, and construction managers to monitor, manage, and reduce the carbon footprint associated with various projects.

• Journal of Power Electronics
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• v.15 no.5
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• pp.1402-1408
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• 2015

A MOSFET's gate driver based on magnetic coupling is investigated. The gate driver can meet the demands in applications for wide range of duty cycles and high frequency. Fully galvanic isolation can be realized, and no auxiliary supply is needed. The driver is insensitive to the leakage inductor of the isolated transformer. No gate resistor is needed to damp the oscillation, and thus the peak output current of the gate driver can be improved. Design of the driving transformer can also be made more flexible, which helps to improve the isolation voltage between the power stage and the control electronics, and aids to enhance the electromagnetic compatibility. The driver's operation principle is analyzed, and the design method for its key parameters is presented. The performance analysis is validated via experiment. The disadvantages of the traditional magnetic coupling and optical coupling have been conquered through the investigated circuit.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.406-406
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• 2010

일반적으로, 나노스케일의 MOS 소자에서는 게이트 절연체 두께가 감소함에 따라 tunneling effect의 증가로 인해 PID (plasma induced damage)로 인한 소자 특성 저하 현상을 감소하는 추세로 알려져 있다. 하지만 요즘 많이 사용되고 있는 high-k 게이트 절연체의 경우에는 오히려 더 많은 charge들이 trapping 되면서 PID가 오히려 더 심각해지는 현상이 나타나고 있다. 이러한 high-k 게이트 식각 시 현재는 주로 Hf-based wet etch나 dry etch가 사용되고 있지만 gate edge 영역에서 high-k 게이트 절연체의 undercut 현상이나 PID에 의한 소자특성 저하가 보고되고 있다. 본 연구에서는 이에 차세대 MOS 소자의 gate stack 구조중 issue화 되고 있는 metal gate 층과 gate dielectric 층의 식각공정에 각각 중성빔 식각과 중성빔 원자층 식각을 적용하여 전기적 손상 없이 원자레벨의 정확한 식각 조절을 해줄 수 있는 새로운 two step 식각 공정에 대한 연구를 진행하였다. 먼저 TiN metal gate 층의 식각을 위해 HBr과 $Cl_2$ 혼합가스를 사용한 중성빔 식각기술을 적용하여 100 eV 이하의 에너지 조건에서 하부층인 $HfO_2$와 거의 무한대의 식각 선택비를 얻었다. 하지만 100 eV 조건에서는 낮은 에너지에 의한 빔 스케터링으로 실제 패턴 식각시 etch foot이 발생되는 현상이 관찰되었으며, 이를 해결하기 위하여 먼저 높은 에너지로 식각을 진행하고 $HfO_2$와의 계면 근처에서 100 eV로 식각을 해주는 two step 방법을 사용하였다. 그 결과 anistropic 하고 하부층에 etch stop된 식각 형상을 관찰할 수 있었다. 다음으로 3.5nm의 매우 얇은 $HfO_2$ gate dielectric 층의 정확한 식각 깊이 조절을 위해 $BCl_3$와 Ar 가스를 이용한 중성빔 원자층 식각기술을 적용하여 $1.2\;{\AA}$/cycle의 단일막 식각 조건을 확립하고 약 30 cycle 공정시 3.5nm 두께의 $HfO_2$ 층이 완벽히 제거됨을 관찰할 수 있었다. 뿐만 아니라, vertical 한 식각 형상 및 향상된 표면 roughness를 transmission electron microscope(TEM)과 atomic force microscope (AFM)으로 관찰할 수 있었다. 이러한 중성빔 식각과 중성빔 원자층 식각기술이 결합된 새로운 gate recess 공정을 실제 MOSFET 소자에 적용하여 기존 식각 방법으로 제작된 소자 결과를 비교해 본 결과 gate leakage current가 약 one order 정도 개선되었음을 확인할 수 있었다.

• Transactions of Materials Processing
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• v.21 no.2
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• pp.96-100
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• 2012

Conventional injection molding system for producing extremely thin-wall parts such as Light Guide Plates(LGP's) for mobile displays is at the limit of its capability due to its tendency to develop frozen layers and the critical speed of injection. The molten polymer in the cavity freezes quickly as its heat is rapidly transferred to the mold base. Many attempts have been tried in the past to overcome this problem. The present study used the injection/compression molding technology to produce a thin-wall part, with enhanced features such as an automated mechanism for cutting gates. As a result, the total cycle time was reduced by almost 35 seconds, resulting in a productivity increase by 30%.

• Journal of information and communication convergence engineering
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• v.11 no.1
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• pp.50-55
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• 2013

In this paper, we propose a parallel intra-operation unit and a memory architecture for improving the performance of intra-prediction, which utilizes spatial correlation in an image to predict the blocks and contains 17 prediction modes in total. The design is targeted for portable devices applying H.264/AVC decoders. For boosting the performance of the proposed design, we adopt a parallel intra-operation unit that can achieve the prediction of 16 neighboring pixels at the same time. In the best case, it can achieve the computation of one luma $16{\times}16$ block within 16 cycles. For one luma $4{\times}4$ block, a mere one cycle is needed to finish the process of computation. Compared with the previous designs, the average cycle reduction rate is 78.01%, and the gate count is slightly reduced. The design is synthesized with the MagnaChip $0.18{mu}m$ library and can run at 125 MHz.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1315-1318
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• 2007

Hafnium dioxide nano film as gate insulator for organic thin film transistors is prepared by atomic layer deposition. Mostly crystalline of $HfO_2$ films can be obtained with oxygen plasma and with water at relatively low temperature of $150^{\circ}C$. $HfO_2$ was deposited as a uniform rate $1.2A^{\circ}/cycle$. The morphology and performances of OTFT will be discussed.

• Proceedings of the KIPE Conference
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• 2002.07a
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• pp.542-545
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• 2002

This paper deals with the optimization inverter design and minimization Conduced EMI noise by customizing IPM(Intelligent Power Module). Generally, In case of IPM, we realized that the trade-off relation between switching loss and spike voltage. Higher gate resistor causes tile lower spike voltage and the higher turn-off switching loss. But we know that the life cycle of inverter and the susceptibility of noise, so we optimized the gate resistor. Proposed method is that optimized the gate resistor suitable for the inverter and motor. The simulation and experimental results show that the spike voltage and Conduced EMI noise can be reduced without the additional circuit.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.463-463
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• 2012

ITRS (international technology roadmap for semiconductors)에 따르면 MOS(metal-oxide-semiconductor)의 CD (critical dimension)가 45 nm node이하로 줄어들면서 poly-Si/$SiO_2$를 대체할 수 있는 poly-Si/metal gate/high-k dielectric이 대두된다고 보고하고 있다. 일반적으로 high-k dielectric를 식각시 anisotropic 한 식각 형상을 형성시키기 위해서 plasma를 이용한 RIE (reactive ion etching)를 사용하고 있지만 PIDs (plasma induced damages)의 하나인 PIED (plasma induced edge damage)의 발생이 문제가 되고 있다. PIED의 원인으로 plasma의 direct interaction을 발생시켜 gate oxide의 edge에 trap을 형성시키므로 그 결과 소자 특성 저하가 보고되고 있다. 그러므로 본 연구에서는 이에 차세대 MOS의 high-k dielectric의 식각공정에 HDP (high density plasma)의 ICP (inductively coupled plasma) source를 이용한 원자층 식각 장비를 사용하여 PIED를 줄일 수 있는 새로운 식각 공정에 대한 연구를 하였다. One-monolayer 식각을 위한 1 cycle의 원자층 식각은 총 4 steps으로 구성 되어 있다. 첫 번째 step은 Langmuir isotherm에 의하여 표면에 highly reactant atoms이나 molecules을 chemically adsorption을 시킨다. 두 번째 step은 purge 시킨다. 세 번째 step은 ion source를 이용하여 발생시킨 Ar low energetic beam으로 표면에 chemically adsorbed compounds를 desorption 시킨다. 네 번째 step은 purge 시킨다. 결과적으로 self limited 한 식각이 이루어짐을 볼 수 있었다. 실제 공정을 MOS의 high-k dielectric에 적용시켜 metal gate/high-k dielectric CMOSFETs의 NCSU (North Carolina State University) CVC model로 구한 EOT (equivalent oxide thickness)는 변화가 없으면서 mos parameter인 Ion/Ioff ratio의 증가를 볼 수 있었다. 그 원인으로 XPS (X-ray photoelectron spectroscopy)로 gate oxide의 atomic percentage의 분석 결과 식각 중 발생하는 gate oxide의 edge에 trap의 감소로 기인함을 확인할 수 있었다.