• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.591-594
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• 2005

This paper describes a design of AES-based CCM Protocol for IEEE 802.11i Wireless LAN Security. The CCMP core is designed with 128-bit data path and iterative structyre which uses 1 clock cycle per round operation. To maximize its performance, two AES cores are used, one is for counter mode for data confidentiality and the other is for CBC(Cipher Block Chaining) mode for authentication and data integrity. The S-box that requires the largest hardware in AES core is implemented using composite field arithmetic, and the gate count is reduced by about 23% compared with conventional LUT-based design. The CCMP core designed in Verilog-HDL has 35,013 gates, and the estimated throughput is about 768Mbps at 66-MHz clock frequency.

• Advances in aircraft and spacecraft science
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• v.4 no.6
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• pp.651-677
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• 2017

For the past ten years' efforts have been made to introduce environmentally-friendly "green" electric-taxi and maneuvering airplane systems. The stated purpose of e-taxi systems is to reduce the taxiing fuel expenses, expedite pushback procedures, reduce gate congestion, reduce ground crew involvement, and reduce noise and air pollution levels at large airports. Airplane-based autonomous traction electric motors receive power from airplane's APU(s) possibly supplemented by onboard batteries. Using additional battery energy storages ads significant inert weight. Systems utilizing nose-gear traction alone are often traction-limited posing serious dispatch problems that could disrupt airport operations. Existing APU capacities are insufficient to deliver power for tractive taxiing while also providing for power off-takes. In order to perform comparative and objective analysis of taxi tractive requirements a "standard" taxiing cycle has been proposed. An analysis of reasonably expected tractive resistances has to account for steepest taxiway and runway slopes, taxiing into strong headwind, minimum required coasting speeds, and minimum acceptable acceleration requirements due to runway incursions issues. A mathematical model of tractive resistances was developed and was tested using six different production airplanes all at the maximum taxi/ramp weights. The model estimates the tractive force, energy, average and peak power requirements. It has been estimated that required maximum net tractive force should be 10% to 15% of the taxi weight for safe and expeditious airport movements. Hence, airplanes can be dispatched to move independently if the operational tractive taxi coefficient is 0.1 or higher.

• Proceedings of the Materials Research Society of Korea Conference
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• 2009.11a
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• pp.23.2-23.2
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• 2009

Atomic layer deposition (ALD)have been proven to be a very attractive technique for the fabrication of advanced gate dielectrics and DRAM insulators due to excellent conformality and precise control of film thickness and composition, However, one major disadvantages of ALD is its relatively low deposition rate (throughput) because the deposition rate is typically limited by the time required for purging process between the introduction of precursors. In order to improve its throughput, many efforts have been made by commercial companies, for example,the modification reactor and development of precursors. However, any promising solution has not reported to date. We developed a new concept ALD system(Lucida TM S200) with high-throughput. In this process, a continuous flow of ALD precursor and purging gas are simultaneously introduced from different locations in the ALD reactor. A cyclic ALD process is carried out by moving the wafer holder up and down. Therefore, the time required for ALD reaction cycle is determined by speed of the wafer holder and vapor pressure of precursors. We will present the operating principle of our system and results of deposition.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.12
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• pp.1554-1563
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• 1999

This paper presents the design of high speed processor for a sequence logic control using field programmable gate array(FPGA). The sequence logic controller is widely used for automating a variety of industrial plants. The FPGA designed by VHDL consists of program and data memory interface block, input and output block, instruction fetch and decoder block, register and ALU block, program counter block, debug control block respectively. Dedicated clock inputs in the FPGA were used for high speed execution, and also the program memory was separated from the data memory for high speed execution of the sequence instructions at 40 MHz clock. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 16 bits or 32 bits respectively. And the real time debug operation was implemented for easy debugging the designed processor. This FPGA was synthesized by pASIC 2 SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to sequence control system with inputs and outputs of 256 points. The designed processor for the sequence logic was compared with the control system using the DSP(TM320C32-40MHz) and conventional PLC system. The designed processor for the sequence logic showed good performance.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.03a
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• pp.107-107
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• 2003

원자층 증착(ALD, Atomic Layer Deposition)기술은 기판 표면에서의 self-limiting reaction을 통해 매우 얇은 박막을 형성할 수 있고, 두께 및 조성 제어를 정확히 할 수 있으며, 복잡한 형상의 기판에서도 100%에 가까운 step coverage를 얻을 수 있어 초미세패턴의 형성과 매우 얇은 두께에서 균일한 물리적, 전기적 특성이 요구되는 초미세 반도체 공정에 적합하다. 특히 반도체의 logic 및 memory 소자의 gate 공정에서 절연막과 보호막으로, 그리고 배선공정에서는 층간절연막(ILD, Inter Layer Dielectric)으로 사용하는 silicon oxide 박막에 적용될 경우, LPCVD 방법에 비해 낮은 온도에서 증착이 가능해 boron과 같은 dopant들의 확산을 최소화하여 transistor 특성 향상이 가능하며, PECVD 방법에 비해 전기적·물리적 특성이 월등히 우수하고 대면적 uniformity 증가가 기대된다. 본 연구에서는 자체적으로 설계 및 제작한 장비를 이용하여 silicon oxide 박막을 ALD 방법으로 증착하고 그 특성을 살펴보았다. 먼저, cycle 수에 따른 증착 박막 두께의 linearity를 통해서 원자층 증착(ALD)임을 확인할 수 있었으며, reactant exposure(L)와 증착 온도에 따른 deposition rate 변화를 알아보았다 Elipsometer를 이용해 증착된 silicon oxide 박막의 두께 및 굴절률과 그 uniformity를 관찰하였고, AES 및 XPS 분석 장비로 박막의 조성비와 불순물 성분을 살펴보았으며, 증착 박막의 치밀성 평가를 위해 HF etchant로 wet etch rate를 측정하여 물리적 특성을 정리하였다. 특히, 기존의 박막 증착 방법인 LPCVD와 PECVD에 의한 silicon oxide박막의 물성과 비교, 평가해 보았다. 나아가 적절한 촉매 물질을 선정하여 원자층 증착(ALD) 공정에 적용하여 그 효과도 살펴보았다.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.67 no.5
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• pp.680-687
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• 2018

Because of its predictability of the energy cycle and huge scale power output, the ocean energy from tidal power utilization has always received attention as a great energy source, even though its development cost, including the embankment construction, is so much higher than that of any other energy source. Nevertheless, nowadays many projects are being planned on account of institutional support from the government and the recent advance of construction technology. In Korea, the new industry field operating and managing the tidal power plant has already opened. But we are facing a number of problems for optimal operation of tidal power plant that are a lack of operation experience and a skill of professional management and others. This paper suggests a novel way to determine the starting head of power generation by generating power comparison method For this new method, the paper discusses many factors including changing the volume of the basin, the number of operating turbines and gates and forecasting the tidal amplitude and the characteristic curve of turbine and gate. Finally we verified that it can increase about 2% an annual power generation compared with the conventional method using the original operational function made in the plant design process.

• Journal of Power Electronics
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• v.18 no.2
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• pp.522-532
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• 2018

The cascaded H Bridge (CHB) multilevel inverter (MLI) is popular among the classical MLI topologies due to its modularity and reliability. Although space vector modulation (SVM) is the most suitable modulation scheme for MLIs, it has not been used widely in industry due to the higher complexity involved in its implementation. In this paper, a simple and novel generalized SVM algorithm is proposed, which has both reduced time and space complexity. The proposed SVM involves the generalization of both the duty cycle calculation and switching sequence generation for any n-level inverter. In order to generate the gate pulses for an inverter, a generalized switch matrix (SM) for the CHB inverter is also introduced, which further simplifies the algorithm. The algorithm is tested and verified for three-phase, three-level and five-level CHB inverters in simulations and hardware implementation. A comparison of the proposed method with existing SVM schemes shows the superiority of the proposed scheme.

• Journal of Power Electronics
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• v.18 no.2
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• pp.395-406
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• 2018

Marine controlled-source electromagnetic transmitters (MCSETs) are important in marine electromagnetic exploration systems. They play a crucial role in the exploration of solid mineral resources, marine oil, and gas and in marine engineering evaluation. A DC-DC controlled-source circuit is typically used in traditional MCSETs, but using this circuit in MCSETs causes several problems, such as large voltage ringing of the high-frequency diode, heating of the insulated-gate bipolar transistor (IGBT) module, high temperature of the high-frequency transformer, loss of the duty cycle, and low transmission efficiency of the controlled-source circuit. This paper presents a clamping-diode circuit for MCSET (CDC-MCSET). Clamping diodes are added to the controlled-source circuit to reduce the loss of the duty ratio and the voltage peak of the high-frequency diode. The temperature of the high-frequency diode, IGBT module, and transformer is decreased, and the service life of these devices is prolonged. The power transmission efficiency of the controlled-source circuit is also improved. Saber simulation and a 20 KW MCSET are used to verify the correctness and effectiveness of the proposed CDC-MCSET.

• Journal of IKEEE
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• v.20 no.4
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• pp.435-438
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• 2016

HEVC CABAC binary arithmetic decoder operates in three decoding modes i.e. regular, bypass, and termination modes, where their decoding operations and time differ a lot. Furthermore, when renormalization occurs, its internal feedback loop induces large delay. In this paper, a binary arithmetic decoder was designed to solve this problem. In advance, it checks all range values with possible renormalization. When renormalization occurs, it immediately updates range value and finishes all calculation in a cycle. When implemented in 0.18 um process technology, its maximum operating frequency and gate counts are 215 MHz and 5,423 gates, respectively.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.1564-1567
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• 2005

Zinc oxide thin films were grown at the t emperature of $100^{\circ}C$ and $150^{\circ}C$ by means of plasma enhanced atomic layer deposition (PEALD) and conventional atomic layer deposition for applying to the transparent thin film transistor (TTFT). The growth rate of $1.9{\AA}/cycle$ with oxygen plasma is similar to that of film grown with water. While the sheet resistivity of ZnO grown with water is 1233 ohm/sq, that of film grown with oxygen plasma was too high to measure with 4 point probe and hall measurement system. The resistivity of the films grown with oxygen plasma estimated to be $10^6$ times larger than that of the films grown with water. The difference of electrical property between two films was caused by the O/Zn atomic ratio. We fabricated ZnO-TFT by means of ALD for the first time and the ZnO channel fabricated with water showed saturation mobility of $0.398cm^2/V{\cdot}s$ with bottom gate configuration.