• 한국정보통신학회논문지
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• 제2권3호
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• pp.431-437
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• 1998

본 논문에서는, ULSI에서 기존의 실리콘 절연막을 대체할 것으로 여겨지는 질화 산화막(NO)과 재산화 질화 산화막(ONO)의 전기적 특성을 조사하였다. 특히, 질화 및 재산화 시간에 따른 NO와 ONO막의 전류전압 특성, 게이트 전압이동, 시간종속 절연항복 특성(TDDB) 변화를 측정하였고, 외부 온도 변화에 따른 최적화 된NO와 ONO막의 누설 전류와 절연체가 항복에 이르게 하는 전하량(Q$\_bd$)변화를 측정하였다. 그런 다음 기존의SIO$\_2$와 비교하였다. 측정 결과로부터, NO와 ONO막은 공정시간에 상당히 의존적이었으며, 최적화된 ONO막은 같은 전계를 유지하는 동안 절연 특성 및 Q$\_bd$특성에서 NO막과 SIO$\_2$에 비하여 우수한 성능을 보였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 추계학술대회 논문집 Vol.17
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• pp.207-209
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• 2004

Currently, for satisfying the needs of scaled MOSFET's a high quality thin oxide dielectric is desired because the properties of conventional $SiO_2$ film are not acceptable for these very small sized transistors. As an alternative gate dielectric have drawn considerable alternation due to their superior performance and reliability properties over conventional $SiO_2$, to obtain the superior characteristics of ultra thin dielectric films, $N_2O$ grown thin oxynitride has been proposed as a dielectric growtuanneal ambient. In this study the authors observed process characteristics of $N_2O$ grown thin dielectric. In view points of the process characteristics of MOS capacitor, the sheet resistance of 4.07$[\Omega/sq.]$, the film stress of $1.009e^{10}[dyne/cm^2]$, the threshold voltage$(V_t)$ of 0.39[V], the breakdown voltage(BV[V]) of 11.45[V] was measured in PMOS. I could achieve improved electrical characteristics and reliability for deep submicron MOSFET devices with $N_2O$ thin oxide.

• 한국전기전자재료학회논문지
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• 제28권4호
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• pp.218-221
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• 2015

Power MOSFETs (metal oxide semiconductor field effect transistor) operate as energy control semiconductor switches. In order to reduce energy loss of the device during switch-on state, it is essential to increase its conductance. In this study we have investigated a structure to reduce the on-resistance characteristics of the MOSFET. We have a proposed MOSFET structure of active cells region buried under the gate pad. The measurement are carried out with a EDS to analyze electrical characteristics, and the proposed MOSFET are compared with the conventional MOSFET. The result of proposed MOSFET was 1.68[${\Omega}$], showing 10% improvement compared to the conventional MOSFET at 700[V].

• 한국항공우주학회지
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• 제42권11호
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• pp.981-987
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• 2014

DC/DC 컨버터는 임의의 직류전원을 부하가 요구하는 형태의 직류전원으로 변환시키는 효율이 높은 전력변환기이다. DC/DC 컨버터는 MOSFET(산화물-반도체 전계 효과 트랜지스터), PWM-IC(펄스폭 변조 집적회로) 제어기, 인덕터, 콘덴서 등으로 구성되어있다. MOSFET는 스위치 기능을 수행하는데 코발트 60 ($^{60}Co$) 저준위 감마발생기를 이용한 TID 실험에서 방사선의 영향으로 문턱전압과 항복전압의 변화와 SEGR 실험에 적용된 5종류의 중이온 입자는 MOSFET의 게이트(gate)에 영향을 주어 게이트가 파괴된다. MOSFET의 TID 실험은 40 Krad 까지 수행하였으며, SEGR 실험은 제어보드를 구현한 후 LET(MeV/mg/$cm^2$)별 cross section($cm^2$)을 연구하는데 있다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 추계학술대회 논문집 전기물성,응용부문
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• pp.71-72
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• 2006

플라스틱 기판 위에 유도 결합 플라즈마 화학적 기상 증착장치 (Inductively Coupled Plasma Chemicai Vapor Deposition, ICP-CVD) 를 사용하여 실리콘 산화막 ($SiO_2$)을 증착하고, 엑시머레이저 어널링 (Excimer Laser Annealing, ELA) 과 $N_{2}O$ 플라즈마 전처리를 통해, 전기용량-전압(Capacitance-Voltage, C-V) 특성과 항복 전압장 (Breakdown Voltage Field) 과 같은 전기적 특성을 개선시켰다. 에너지 밀도 $250\;mJ/cm^2$ 의 엑시머 레이저 어닐링은 실리콘 산화막의 평탄 전압 (Flat Band Voltage) 을 0V에 가까이 이동시키고, 유효 산화 전하밀도 (Effective Oxide Charge Density)를 크게 감소시킨다. $N_{2}O$ 플라즈마 전처리를 통해 항복 전압장은 6MV/cm 에서 9 MV/cm 으로 향상된다. 엑시머 레이저 어닐링과 $N_{2}O$ 플라즈마 전처리를 통해 평탄 전압은 -9V 에서 -1.8V 로 향상되고, 유효 전하 밀도 (Effective Charge Density) 는 $400^{\circ}C$에서 TEOS 실리콘 산화막을 증착하는 경우의 유효 전하 밀도 수준까지 감소한다.

• 한국컴퓨터산업교육학회:학술대회논문집
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• 한국컴퓨터산업교육학회 2003년도 제4회 종합학술대회 논문집
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• pp.71-74
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• 2003

A vertical trench electrode type EST has been proposed in this paper. The proposed device considerably improve the snap-back effect which leads to a lot of problem of device applications. In this paper, the vertical dual gate Emitter Switched Thyristor(EST) with trench electrode has been proposed for improving snap-back effect. It is observed that the forward blocking voltage of the proposed device is 800V. The conventional EST of the same size were no more than 633V. Because the proposed device was constructed of trench-type electrode, the electric field moved toward trench-oxide layer, and the punch through breakdown of the proposed EST is occurred at latest.

• 한국표면공학회지
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• 제29권6호
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• pp.809-815
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• 1996

$Y_2O_3$-based metal-insulator-semiconductor (MIS) structure on p-Si(100) has been studied. Films were prepared by UHV reactive ionized cluster beam deposition (r-ICBD) system. The base pressure of the system was about $1 \times 10^{-9}$ -9/ Torr and the process pressure $2 \times 10^{-5}$ Torr in oxygen ambience. Glancing X-ray diffraction(GXRD) and in-situ reflection high energy electron diffracton(RHEED) analyses were performed to investigate the crystallinity of the films. The results show phase change from amorphous state to crystalline one with increasingqr acceleration voltage and substrate temperature. It is also found that the phase transformation from $Y_2O_3$(111)//Si(100) to $Y_2O_3$(110)//Si(100) in growing directions takes place between $500^{\circ}C$ and $700^{\circ}C$. Especially as acceleration voltage is increased, preferentially oriented crystallinity was increased. Finally under the condition of above substrate temperature $700^{\circ}C$ and acceleration voltage 5kV, the $Y_2O_3$films are found to be grown epitaxially in direction of $Y_2O_3$(1l0)//Si(100) by observation of transmission electron microscope(TEM). Capacitance-voltage and current-voltage measurements were conducted to characterize Al/$Y_2O_3$/Si MIS structure with varying acceleration voltage and substrate temperature. Deposited $Y_2O_3$ films of thickness of nearly 300$\AA$ show that the breakdown field increases to 7~8MV /cm at the same conditon of epitaxial growing. These results also coincide with XPS spectra which indicate better stoichiometric characteristic in the condition of better crystalline one. After oxidation the breakdown field increases to 13MV /cm because the MIS structure contains interface silicon oxide of about 30$\AA$. In this case the dielectric constant of only $Y_2O_3$ layer is found to be $\in$15.6. These results have demonstrated the potential of using yttrium oxide for future VLSI/ULSI gate insulator applications.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.267-270
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• 2001

A new small scaling Lateral Trench Insulated Gate Bipolar Transistor (SSLTIGBT) was proposed to improve the characteristics of the device. The entire electrode of the LTIGBT was replaced with a trench-type electrode. The LTIGBT was designed so that the width of device was no more than 10$\mu\textrm{m}$. The latch-up current densities were improved by 4.5 and 7.6 times, respectively, compared to those of the same sifted conventional LTIGBT and the conventional LTIGBT which has the width of 17$\mu\textrm{m}$. The enhanced latch-up capability of the SSLTIGBT was obtained due to the fact that the hole current in the device reaches the cathode via the p+ cathode layer underneath the n+ cathode layer, directly. The forward blocking voltage of the SSLTIGBT was 125 V. At the same size, those of the conventional LTIGBT and the conventional LTIGBT with the width of 17$\mu\textrm{m}$ were 65 V and 105 V, respectively. Because the proposed device was constructed of trench-type electrodes, the electric field in the device were crowded to trench oxide. Thus, the punch through breakdown of LTEIGBT occurred late.

• Transactions on Electrical and Electronic Materials
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• 제2권4호
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• pp.15-18
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• 2001

A new small scaling Lateral Trench Insulated Gate Bipolar Transistor (SSLTIGBT) was proposed to improve the characteristics of the device. The entire electrode of the LTIGBT was replaced with a trench-type electrode. The LTIGBT was designed so that the width of device was no more than 10 ${\mu}{\textrm}{m}$. The latch-up current densities were improved by 4.5 and 7.6 times, respectively, compared to those of the same sized conventional LTIGBT arid the conventional LTIGBT which has the width of 17 ${\mu}{\textrm}{m}$. The enhanced latch-up capability of the SSLTIGBT was obtained due to the fact that the hole current in the device reaches the cathode via the p+ cathode layer underneath the n+ cathode layer, directly. The forward blocking voltage of the SSLTIGBT was 125 V. At the same size, those of the conventional LTIGBT and the conventional LTIGBT with the width of 17 ${\mu}{\textrm}{m}$ were 65 V and 105 V, respectively. Because the proposed device was constructed of trench-type electrodes, the electric field In the device were crowded to trench oxide. Thus, the punch through breakdown of LTEIGBT occurred late.

• 한국전기전자재료학회논문지
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• 제36권4호
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• pp.413-417
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• 2023

Gallium Oxide (Ga₂O₃) is preferred as a material for next generation power semiconductors. The Ga₂O₃ should solve the disadvantages of low thermal resistance characteristics and difficulty in forming an inversion layer through p-type ion implantation. However, Ga₂O₃ is difficult to inject p-type ions, so it is being studied in a heterojunction structure using p-type oxides, such as NiO, SnO, and Cu₂O. Research the lateral-type FET structure of NiO/Ga₂O₃ heterojunction under the Gate contact using the Sentaurus TCAD simulation. At this time, the VG-ID and VD-ID curves were identified by the thickness of the Epi-region (channel) and the doping concentration of NiO of 1×10¹⁷ to 1×10¹⁹ cm-3. The increase in Epi region thickness has a lower threshold voltage from -4.4 V to -9.3 V at I_D = 1×10^-8 mA/mm, as current does not flow only when the depletion of the PN junction extends to the Epi/Sub interface. As an increase of NiO doping concentration, increases the depletion area in Ga₂O₃ region and a high electric field distribution on PN junction, and thus the breakdown voltage increases from 512 V to 636 V at I_D =1×10^-3 A/mm.