• Journal of the Optical Society of Korea
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• 제18권5호
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• pp.477-484
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• 2014

In this paper, we propose a new optical secret key sharing method based on the Diffie-Hellman key exchange protocol required in cipher system. The proposed method is optically implemented by using a free-space interconnected optical logic gate technique in order to process XOR logic operations in parallel. Also, we present a compact type of optical module which can perform the modified Diffie-Hellman key exchange for a cryptographic system. Schematically, the proposed optical configuration has an advantage of producing an open public key and a shared secret key simultaneously. Another advantage is that our proposed key exchange system uses a similarity to double key encryption techniques to enhance security strength. This can provide a higher security cryptosystem than the conventional Diffie-Hellman key exchange protocol due to the complexity of the shared secret key. Results of numerical simulation are presented to verify the proposed method and show the effectiveness in the modified Diffie-Hellman key exchange system.

• 한국컴퓨터정보학회논문지
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• 제13권6호
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• pp.195-201
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• 2008

이동식 시스템의 보안관련 문제점 등을 해결하기 위하여 본 논문은 네트워크 환경과 유무선 통신망에 적합하며 구현의 용이성, 비도 유지, 재수정 및 재사용 할 수 있으며 TCP/IP 프로토콜 아키텍쳐에 적합한 이동식 스마트카드용 MT-Serpent 암호알고리즘을 소프트웨어 기반이 아닌 하드웨어 기반 칩 레벨로 구현하였다. 구현된 MT-Serpent 암호시스템은 크기면에서 4,032이고 throughput은 406.2Mbps@2.44MHz를 가진다. 구현된 MT-Serpent 암호알고리즘은 스마트카드 등과 같은 이동식 시스템의 특징을 살릴 수 있도록 하기 위하여 TCP/IP 프로토콜의 보안 취약성을 보강하며 유무선 환경에서 여러 종류의 서비스가 가능하고 다수의 사용자에 대한 보안을 유지하는데 주요한 목적이 있다.

• 전기학회논문지P
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• 제67권1호
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• pp.9-14
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• 2018

In this paper, we introduce an AES-based security chip for the embedded system of Internet of Things(IoT). We used Verilog HDL to implement the AES algorithm in FPGA. The designed AES module creates 128-bit cipher by encrypting 128-bit plain text and vice versa. RTL simulations are performed to verify the AES function and the theory is compared to the results. An FPGA emulation was also performed with 40 types of test sequences using two Altera DE0-Nano-SoC boards. To evaluate the performance of security algorithms, we compared them with AES implemented by software. The processing cycle per data unit of hardware implementation is 3.9 to 7.7 times faster than software implementation. However, there is a possibility that the processing speed grow slower due to the feature of the hardware design. This can be solved by using a pipelined scheme that divides the propagation delay time or by using an ASIC design method. In addition to the AES algorithm designed in this paper, various algorithms such as IPSec can be implemented in hardware. If hardware IP design is set in advance, future IoT applications will be able to improve security strength without time difficulties.

• ETRI Journal
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• 제28권3호
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• pp.320-328
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• 2006

Using biometrics to verify a person's identity has several advantages over the present practice of personal identification numbers (PINs) and passwords. To gain maximum security in a verification system using biometrics, the computation of the verification as well as the storing of the biometric pattern has to take place in a smart card. However, there is an open issue of integrating biometrics into a smart card because of its limited resources (processing power and memory space). In this paper, we propose a speaker verification algorithm using a support vector machine (SVM) with a very few features, and implemented it on a 32-bit smart card. The proposed algorithm can reduce the required memory space by a factor of more than 100 and can be executed in real-time. Also, we propose a hardware design for the algorithm on a field-programmable gate array (FPGA)-based platform. Based on the experimental results, our SVM solution can provide superior performance over typical speaker verification solutions. Furthermore, our FPGA-based solution can achieve a speed-up of 50 times over a software-based solution.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제17권1호
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• pp.97-119
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• 2023

The number of industrial Internet of Things (IoT) users is increasing rapidly. Lightweight block ciphers have started to be used to protect the privacy of users. Hardware-oriented security design should fully consider the use of fewer hardware devices when the function is fully realized. Thus, this paper designs a lightweight block cipher IIoTBC for industrial IoT security. IIoTBC system structure is variable and flexibly adapts to nodes with different security requirements. This paper proposes a 4×4 S-box that achieves a good balance between area overhead and cryptographic properties. In addition, this paper proposes a preprocessing method for 4×4 S-box logic gate expressions, which makes it easier to obtain better area, running time, and power data in ASIC implementation. Applying it to 14 classic lightweight block cipher S-boxes, the results show that is feasible. A series of performance tests and security evaluations were performed on the IIoTBC. As shown by experiments and data comparisons, IIoTBC is compact and secure in industrial IoT sensor nodes. Finally, IIoTBC has been implemented on a temperature state acquisition platform to simulate encrypted transmission of temperature in an industrial environment.

• 시스템엔지니어링학술지
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• 제14권2호
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• pp.73-82
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• 2018

In this work, a hardware based cryptographic module for the cyber security of nuclear power plant is developed using a system engineering approach. Nuclear power plants are isolated from the Internet, but as shown in the case of Iran, Man-in-the-middle attacks (MITM) could be a threat to the safety of the nuclear facilities. This FPGA-based module does not have an operating system and it provides protection as a firewall and mitigates the cyber threats. The encryption equipment consists of an encryption module, a decryption module, and interfaces for communication between modules and systems. The Advanced Encryption Standard (AES)-128, which is formally approved as top level by U.S. National Security Agency for cryptographic algorithms, is adopted. The development of the cyber security module is implemented in two main phases: reverse engineering and re-engineering. In the reverse engineering phase, the cyber security plan and system requirements are analyzed, and the AES algorithm is decomposed into functional units. In the re-engineering phase, we model the logical architecture using Vitech CORE9 software and simulate it with the Enhanced Functional Flow Block Diagram (EFFBD), which confirms the performance improvements of the hardware-based cryptographic module as compared to software based cryptography. Following this, the Hardware description language (HDL) code is developed and tested to verify the integrity of the code. Then, the developed code is implemented on the FPGA and connected to the personal computer through Recommended Standard (RS)-232 communication to perform validation of the developed component. For the future work, the developed FPGA based encryption equipment will be verified and validated in its expected operating environment by connecting it to the Advanced power reactor (APR)-1400 simulator.

• International Journal of Contents
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• 제11권4호
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• pp.70-76
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• 2015

The development of technology provides and increases security as well as convenience for humans. The development of new technology directly affects the standard of life thanks to smart home automatic control systems. This paper describes a door control, automatic curtain, home security (CCTV, fire, gas, safe, etc.), home control (energy, light, ventilation, etc.) and web-based smart home automatic controller. It also describes the use of ARM (Advanced RISC Machines) for automatic control of home equipment, a Multi-Axes Servo Controller using FPGA (Field Programmable Gate Array) and PLC (programmable logic controller). Additionally, it describes the development of a HTML editor using web auto control software. The tab loading time (7 seconds) is faster when using ARM-based web browser software instead of Chrome and Firefox is used because the browser has a small memory footprint (300M). This system is realized by web auto controller language which controls and uses PLCs that are easier than existing devices. This smart home automatic control technology can control smart home equipment anywhere and anytime and provides a remote interface through mobile equipment.

• 대한원격탐사학회지
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• 제34권4호
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• pp.579-590
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• 2018

Shipping of North Korea is not yet publicly well documented. Taedong River, the most important sea route of North Korea, is selected as a model study area to show how effectively a remote place can be investigated through the application of satellite-based Automatic Identification System (S-AIS) for understanding shipping and tracks of vessels which passed the lock gate in the Taedong River and visited the nearby ports on its track. S-AIS data of the year 2014 were analyzed on the basis of various time periods, country of registry and category of ships. A total of 325 vessels were observed. The ships under the flags of North Korea, Cambodia and Sierra Leone were found to be dominant in frequencies which accounted for 43.08%, 16.00%, and 8.92%, respectively. Trajectories of the 325 ships in the Yellow Sea were also checked according to the flags. It is concluded that some ships under the flags of Cambodia, Sierra Leone, Mongolia, Panama and Kiribati are regarded as flags of convenience, and ships without flag and ship type codes also comprised a remarkable portion out of the total ships.

• 정보보호학회논문지
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• 제28권5호
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• pp.1225-1231
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• 2018

FPGA(Field Programmable Gate Array)를 이용한 시스템 개발은 개발 시간 단축 및 비용 절감을 위해 제3자에게 아웃소싱하는 형태로 발전하고 있다. 이러한 과정에서 악의적인 기능 및 오작동을 유발하는 하드웨어 악성기능(Hardware Trojan)이 시스템에 유입될 위협 또한 증가하고 있다. 하드웨어 악성기능의 탐지를 위해 다양한 방법들이 제시되고 있으나 FPGA에 탑재되는 비트스트림을 직접 수정하는 형태의 하드웨어 악성기능은 기존에 제시된 방법으로 탐지하기 어렵다. 이러한 유형의 하드웨어 악성기능 탐지를 위해서는 비트스트림으로부터 구현된 회로를 식별 가능한 수준으로 역공학하는 과정이 필요하며, 회로를 구성하는 여러 요소 중 특히 신호의 입출력 흐름을 파악할 수 있는 연결 정보를 역공학하는 것이 중요하다. 본 논문에서는 FPGA 비트스트림으로부터 연결 정보를 복구하는 도구인 BIL을 분석하고 이를 개선하기 위한 방법을 제시한다.

• Nuclear Engineering and Technology
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• 제53권10호
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• pp.3327-3334
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• 2021

Present electric grids are advanced to integrate smart grids, distributed resources, high-speed sensing and control, and other advanced metering technologies. Cybersecurity is one of the challenges of the smart grid and nuclear plant digital system. It affects the advanced metering infrastructure (AMI), for grid data communication and controls the information in real-time. The research article is emphasized solving the nuclear and smart grid hardware security issues with the integration of field programmable gate array (FPGA), and implementing the latest Time Authenticated Cryptographic Identity Transmission (TACIT) cryptographic algorithm in the chip. The cryptographic-based encryption and decryption approach can be used for a smart grid distribution system embedding with FPGA hardware. The chip design is carried in Xilinx ISE 14.7 and synthesized on Virtex-5 FPGA hardware. The state of the art of work is that the algorithm is implemented on FPGA hardware that provides the scalable design with different key sizes, and its integration enhances the grid hardware security and switching. It has been reported by similar state-of-the-art approaches, that the algorithm was limited in software, not implemented in a hardware chip. The main finding of the research work is that the design predicts the utilization of hardware parameters such as slices, LUTs, flip-flops, memory, input/output blocks, and timing information for Virtex-5 FPGA synthesis before the chip fabrication. The information is extracted for 8-bit to 128-bit key and grid data with initial parameters. TACIT security chip supports 400 MHz frequency for 128-bit key. The research work is an effort to provide the solution for the industries working towards embedded hardware security for the smart grid, power plants, and nuclear applications.