• Current Optics and Photonics
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• v.3 no.6
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• pp.531-540
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• 2019

Spectral Amplitude Coding Optical Code Division Multiple Access (SAC OCDMA) is an advanced technique in asynchronous environments. This paper proposes design and implementation of a novel quantum logic gate (QLG) code, with code construction algorithm generated without following any code mapping procedures for SAC system. The proposed code has a unitary matrices property with maximum overlap of one chip for various clients and no overlaps in spectra for the rest of the subscribers. Results indicate that a single algorithm produces the same length increment for codes with weight greater than two and follows the same signal to noise ratio (SNR) and bit error rate (BER) calculations for a higher number of users. This paper further examines the performance of a QLG code based SAC-OCDMA system with NAND and direct detection techniques. BER analysis was carried out for the proposed code and results were compared with existing MDW, RD and GMP codes. We demonstrate that the QLG code based system performs better in terms of cardinality, which is followed by improved BER. Numerical analysis reveals that for error free transmission (10^-9), the suggested code supports approximately 170 users with code weight 4. Our results also conclude that the proposed code provides improvement in the code construction, cross-correlation and minimization of noises.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.1
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• pp.52-62
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• 2004

In this paper we look at the effect of Fringe-Enhanced-Barrier-lowering (FEBL) for high-K dielectric MOSFETs and the dependence of FEBL on various technological parameters (spacer dielectrics, overlap length, dielectric stack, S/D junction depth and dielectric thickness). We show that FEBL needs to be contained in order to maintain the performance advantage with scaled high-K dielectric MOSFETs. The degradation in high-K dielectric MOSFETs is also identified as due to the additional coupling between the drain-to-source that occurs through the gate insulator, when the gate dielectric constant is significantly higher than the silicon dielectric constant. The technology parameters required to minimize the coupling through the high-K dielectric are identified. It is also shown that gate dielectric stack with a low-K material as bottom layer (very thin $SiO_2$ or oxy-nitride) will be helpful in minimizing FEBL. The circuit performance issues with high-K MOS transistors are also analyzed in this paper. An optimum range of values for the dielectric constant has been identified from the delay and the energy dissipation point of view. The dependence of the optimum K for different technology generations has been discussed. Circuit models for the parasitic capacitances in high-K transistors, by incorporating the fringing effects, have been presented.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.470-473
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• 2002

A communication-aid circuit to detect eye-gazed patterns is proposed in this paper. The circuit is an analog-digital mixed system. By determining the direction of eye-gazed pattern, the circuit detects an eye-gazed pattern from 2-dimensional arrayed patterns on a syllabary. Different from conventional systems, the syllabary is moved to overlap the eye-gazed pattern with the center coordinate of screen. Thus, the proposed circuit can avoid a complex calculation of the distance between the eye-gazed point and the center coordinate. Furthermore: an economical size of hardware can be provided since no full-adders are required by employing floating-gate MOSFBT's. The validity of the cricuit design is confirmed by computer simulations. Furthermore, to implement onto an IC chip, the layout design is performed by using a CAD tool, MAGIC.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07a
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• pp.15-20
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• 2005

We have achieved 180-degree angle of view performance using Super-PVA (S-PVA) technology first time in TFT-LCD industry. 82" full high definition ($1920{\times}1080$) TFT- LCD panel, the world's largest TFT-LCD, have been developed. In addition to the size breakthrough, this product achieves 600nits brightness, over 1200:1 contrast ratio, viewing angle free, 92% color gamut, and 8ms response time. Several key enabling technologies were developed to achieve these specifications, including two transistor direct driven independently controlled S-PVA subpixels, non even area ratio sub-pixels for optimal offaxis gamma, gate overlap driving for larger driving margin, new CCFL technology for higher color gamut, and advanced fabrication techniques including the use of Samsung's new $7^{th}$ generation line.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.4
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• pp.237-250
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• 2015

This paper describes a hardware-oriented algorithm and its conceptual implementation in a real-time speed limit traffic sign detection system on an automotive-oriented field-programmable gate array (FPGA). It solves the training and color dependence problems found in other research, which saw reduced recognition accuracy under unlearned conditions when color has changed. The algorithm is applicable to various platforms, such as color or grayscale cameras, high-resolution (4K) or low-resolution (VGA) cameras, and high-end or low-end FPGAs. It is also robust under various conditions, such as daytime, night time, and on rainy nights, and is adaptable to various countries' speed limit traffic sign systems. The speed limit traffic sign candidates on each grayscale video frame are detected through two simple computational stages using global luminosity and local pixel direction. Pipeline implementation using results-sharing on overlap, application of a RAM-based shift register, and optimization of scan window sizes results in a small but high-performance implementation. The proposed system matches the processing speed requirement for a 60 fps system. The speed limit traffic sign recognition system achieves better than 98% accuracy in detection and recognition, even under difficult conditions such as rainy nights, and is implementable on the low-end, low-cost Xilinx Zynq automotive Z7020 FPGA.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.9 no.6
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• pp.1581-1584
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• 2008

In dual-polycide-gate structure with butting contact, net doping concentration of polysilicon was decreased due to overlap between $n^+$ and $p^+$ and lateral dopant diffusion in silicide/polysilicon layers. The generation of parasitic Schottky diode in butting contact region is attributed both to the $CoSi_2$-loss due to $CoSi_2$ agglomeration and to the decrease in net doping concentration of polysilicon layer. Parasitic Schottky diode reduces noise margin of sense amplifier in DDI DRAM, which causes column fail. The column fail could be reduced by physical isolation of $n^+/p^+$ polysilicon junction or suppressing $CoSi_2$ agglomeration by using nitrogen implantation into $p^+$ polysilicon before $CoSi_2$ formation.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2005.11a
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• pp.353-356
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• 2005

In this paper, the proposed $gamma({\gamma})$ line system is developed for reducing the error between non-linear gamma curve produced by a formula and result produced by hardware implementation. The proposed algorithm and system is based on the specific gamma value 2.2, namely the formula is represented by {0,1}$^{2.2}$ and the bit width of input and out data is 10bit. In order to reduce the error, the system is using least squares polynomial of the numerical method which is calculating the best fitting polynomial through a set of points. The proposed gamma line is consisting of nine kinds of quadratic equations, each with their own overlap sections to get more precise. Based on the algorithm verified by $MATLAB^{TM}$ 7.0, the proposed system is implemented by using Verilog-HDL. The proposed system has 2 clock latency; 1 result per clock. The error range (LSB) is -4 and +3. Its standard deviation is 1.287956238. The total gate count of system is 2,083 gates and the maximum timing is 15.56[ns].

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.2
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• pp.265-272
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• 2007

This proposed gamma (${\gamma}$) correction system is developed to reduce the difference between non-linear gamma curve produced by a typical formula and result produced by the proposed algorithm. In order to reduce the difference, the proposed system is using the Least Squares Polynomial which is calculating the best fitting polynomial through a set of points which is sampled. Each system is consisting of continuous several kinds of equations and having their own overlap sections to get more precise. Based on the algorithm verified by MATLAB, the proposed systems are implemented by using Verilog-HDL. This paper will compare the previous algorithm of gamma system such as Existing system with Seed Table with the latest that such as Proposed system. The former and the latter system have 1, 2 clock latency; each 1 result per clock. Because each of the error range (LSB) is $1{\sim}+1,\;0{\sim}+36$, we can how that Proposed system is improved. Under the condition of SAMSUNG STD90 0.35 worst case, each gate count is 2,063, 2,564 gates and each maximum data arrival time is 29.05[ns], 17.52[ns], respectively.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.51 no.3
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• pp.134-140
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• 2002

Deep submicron NMOSFETs with elevated source/drain can be fabricated using self-aligned selective epitaxial growth(SEG) of silicon for enhanced device characteristics with shallow junction compared to conventional MOSFETs. Shallow junctions, especially with the heartily-doped S/D residing in the elevated layer, give hotter immunity to Yt roll off, drain-induced-barrier-lowering (DIBL), subthreshold swing (SS), punch-through, and hot carrier effects. In this paper, the characteristics of both deep submicron elevated source/drain NMOSFETs and conventional NMOSFETs were investigated by using TSUPREM-4 and MEDICI simulators, and then the results were compared. It was observed from the simulation results that deep submicron elevated S/D NMOSFETs having shallower junction depth resulted in reduced short channel effects, such as DIBL, SS, and hot carrier effects than conventional NMOSFETs. The saturation current, Idsat, of the elevated S/D NMOSFETs was higher than conventional NMOSFETs with identical device dimensions due to smaller sheet resistance in source/drain regions. However, the gate-to-drain capacitance increased in the elevated S/D MOSFETs compared with the conventional NMOSFETs because of increasing overlap area. Therefore, it is concluded that elevated S/D MOSFETs may result in better device characteristics including current drivability than conventional NMOSFETs, but there exists trade-off between device characteristics and fate-to-drain capacitance.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.5-5
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• 2009

Thin-film-transistors (TFTs) that can be prepared at low temperatures have attracted much attention because of the great potential for transparent and flexible electronics. One of the mainstreams in this field is the use of organic semiconductors such as pentacene. But device performance of the organic TFTs is still limited due to low field-effect mobility and rapid degradation after exposing to air. Alternative approach is the use of amorphous oxide semiconductors as a channel. Amorphous oxide semiconductors (AOSs) based TFTs showed the fast technological development, because AOS films can be fabricated at room temperature and exhibit the possibility in application like flexible display, electronic paper, and larges solar cells. Among the various AOSs, a-IGZO has lots of advantages because it has high channel mobility, uniform surface roughness and good transparency. [1] The high mobility is attributed to the overlap of spherical s-orbital of the heavy post-transition metal cations. This study demonstrated the effect of the variation in channel thickness from 30nm to 200nm on the TFT device performance. When the thickness was increased, turn-on voltage and subthreshold swing was decreased. The a-IGZO channels and source/drain metals were deposited with shadow mask. The a-IGZO channel layer was deposited on $SiO_2$/p-Si substrates by RF magnetron sputtering, where RF power is 150W. And working pressure is 3m Torr, at $O_2/Ar$ (2/28 sccm) atmosphere. The electrodes were formed with electron-beam evaporated Ti (30 nm) and Au (70 nm) bilayer. Finally, Al (150nm) as a gate metal was thermal-evaporated. TFT devices were heat-treated in a furnace at 250 $^{\circ}C$ and nitrogen atmosphere for 1hour. The electrical properties of the TFTs were measured using a probe-station. The TFT with channel thickness of 150nm exhibits a good subthreshold swing (SS) of 0.72 V/decade and on-off ratio of $1{\times}10^8$. The field effect mobility and threshold voltage were evaluated as 7.2 and 8 V, respectively.