• Current Optics and Photonics
• /
• 제3권6호
• /
• pp.531-540
• /
• 2019

Spectral Amplitude Coding Optical Code Division Multiple Access (SAC OCDMA) is an advanced technique in asynchronous environments. This paper proposes design and implementation of a novel quantum logic gate (QLG) code, with code construction algorithm generated without following any code mapping procedures for SAC system. The proposed code has a unitary matrices property with maximum overlap of one chip for various clients and no overlaps in spectra for the rest of the subscribers. Results indicate that a single algorithm produces the same length increment for codes with weight greater than two and follows the same signal to noise ratio (SNR) and bit error rate (BER) calculations for a higher number of users. This paper further examines the performance of a QLG code based SAC-OCDMA system with NAND and direct detection techniques. BER analysis was carried out for the proposed code and results were compared with existing MDW, RD and GMP codes. We demonstrate that the QLG code based system performs better in terms of cardinality, which is followed by improved BER. Numerical analysis reveals that for error free transmission (10^-9), the suggested code supports approximately 170 users with code weight 4. Our results also conclude that the proposed code provides improvement in the code construction, cross-correlation and minimization of noises.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제4권1호
• /
• pp.52-62
• /
• 2004

In this paper we look at the effect of Fringe-Enhanced-Barrier-lowering (FEBL) for high-K dielectric MOSFETs and the dependence of FEBL on various technological parameters (spacer dielectrics, overlap length, dielectric stack, S/D junction depth and dielectric thickness). We show that FEBL needs to be contained in order to maintain the performance advantage with scaled high-K dielectric MOSFETs. The degradation in high-K dielectric MOSFETs is also identified as due to the additional coupling between the drain-to-source that occurs through the gate insulator, when the gate dielectric constant is significantly higher than the silicon dielectric constant. The technology parameters required to minimize the coupling through the high-K dielectric are identified. It is also shown that gate dielectric stack with a low-K material as bottom layer (very thin $SiO_2$ or oxy-nitride) will be helpful in minimizing FEBL. The circuit performance issues with high-K MOS transistors are also analyzed in this paper. An optimum range of values for the dielectric constant has been identified from the delay and the energy dissipation point of view. The dependence of the optimum K for different technology generations has been discussed. Circuit models for the parasitic capacitances in high-K transistors, by incorporating the fringing effects, have been presented.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2002년도 ITC-CSCC -1
• /
• pp.470-473
• /
• 2002

A communication-aid circuit to detect eye-gazed patterns is proposed in this paper. The circuit is an analog-digital mixed system. By determining the direction of eye-gazed pattern, the circuit detects an eye-gazed pattern from 2-dimensional arrayed patterns on a syllabary. Different from conventional systems, the syllabary is moved to overlap the eye-gazed pattern with the center coordinate of screen. Thus, the proposed circuit can avoid a complex calculation of the distance between the eye-gazed point and the center coordinate. Furthermore: an economical size of hardware can be provided since no full-adders are required by employing floating-gate MOSFBT's. The validity of the cricuit design is confirmed by computer simulations. Furthermore, to implement onto an IC chip, the layout design is performed by using a CAD tool, MAGIC.

• 한국정보디스플레이학회:학술대회논문집
• /
• 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.I
• /
• pp.15-20
• /
• 2005

We have achieved 180-degree angle of view performance using Super-PVA (S-PVA) technology first time in TFT-LCD industry. 82" full high definition ($1920{\times}1080$) TFT- LCD panel, the world's largest TFT-LCD, have been developed. In addition to the size breakthrough, this product achieves 600nits brightness, over 1200:1 contrast ratio, viewing angle free, 92% color gamut, and 8ms response time. Several key enabling technologies were developed to achieve these specifications, including two transistor direct driven independently controlled S-PVA subpixels, non even area ratio sub-pixels for optimal offaxis gamma, gate overlap driving for larger driving margin, new CCFL technology for higher color gamut, and advanced fabrication techniques including the use of Samsung's new $7^{th}$ generation line.

• IEIE Transactions on Smart Processing and Computing
• /
• 제4권4호
• /
• pp.237-250
• /
• 2015

This paper describes a hardware-oriented algorithm and its conceptual implementation in a real-time speed limit traffic sign detection system on an automotive-oriented field-programmable gate array (FPGA). It solves the training and color dependence problems found in other research, which saw reduced recognition accuracy under unlearned conditions when color has changed. The algorithm is applicable to various platforms, such as color or grayscale cameras, high-resolution (4K) or low-resolution (VGA) cameras, and high-end or low-end FPGAs. It is also robust under various conditions, such as daytime, night time, and on rainy nights, and is adaptable to various countries' speed limit traffic sign systems. The speed limit traffic sign candidates on each grayscale video frame are detected through two simple computational stages using global luminosity and local pixel direction. Pipeline implementation using results-sharing on overlap, application of a RAM-based shift register, and optimization of scan window sizes results in a small but high-performance implementation. The proposed system matches the processing speed requirement for a 60 fps system. The speed limit traffic sign recognition system achieves better than 98% accuracy in detection and recognition, even under difficult conditions such as rainy nights, and is implementable on the low-end, low-cost Xilinx Zynq automotive Z7020 FPGA.

• 한국산학기술학회논문지
• /
• 제9권6호
• /
• pp.1581-1584
• /
• 2008

버팅 콘택을 가진 쌍극 폴리사이드 게이트 구조에서 폴리실리콘 내의 순 도핑(net doping) 농도는 $n^+/p^+$ 중첩 및 실리사이드/폴리실리콘 층에서 도펀트의 수평 확산에 기인하여 감소하였다. 버팅 콘택 영역에서의 쇼트키 다이오드 형성은 $CoSi_2$의 열적 응집 현상에 의한 $CoSi_2$ 손실과 폴리실리콘 내의 농도 저하에 기인된다. DDI DRAM에서 기생 쇼트키 다이오드는 감지 증폭기의 노이즈 마진을 감소시켜 column성 불량을 일으킨다. Column성 불량은 $n^+/p^+$ 폴리실리콘 접합 부분을 물리적으로 분리시키거나, $CoSi_2$ 형성 전 질소 이온을 $p^+$ 영역에 주입 시켜 $CoSi_2$의 응집현상을 억제함으로써 줄일 수 있다.

• 융합신호처리학회 학술대회논문집
• /
• 한국신호처리시스템학회 2005년도 추계학술대회 논문집
• /
• pp.353-356
• /
• 2005

이 논문에서, 제시된 감마$({\gamma})$ 라인 시스템은 해당 공식에 의해 만들어진 비선형 감마 곡선과 하드웨어로 구현된 결과 사이의 오차를 최소화하기 위해 만들어졌다. 제시된 알고리즘과 시스템은 특정 감마값이 2.2, 즉 {0,1}$^{2.2}$에 의해 생성되는 공식과 입, 출력 데이터 크기가 10bit를 기반으로 한다. 오차를 최소화하기 위해, 시스템은 데이터 점들 사이를 지나 적합한 다항식을 만드는 수치해석 방법, 최소 자승 다항식을 사용하였다. 제한된 감마 라인은, 정밀도를 높이기 위해, 서로 각각의 중첩된 범위를 가지는 2차 다항식 9개로 구성되어 있다. $MATLAB^{TM}$ 7.0으로 검증된 알고리즘을 바탕으로, 제한된 시스템은 Verilog-HDL으로 구현되었다. 시스템은 2클럭 지연을 가지며 1 클럭마다 결과가 생성된다. 오차 범위(LSB)는 -4에서 +3이다. 표준편차는 1.287956238을 가진다. 시스템의 전체 게이트 값은 2,083이며, 최대 타이밍은 15.56[ns] 이다.

• 한국정보통신학회논문지
• /
• 제11권2호
• /
• pp.265-272
• /
• 2007

본 논문은 비선형 휘도 출력을 요구하는 영상장치 기기를 위한 감마 보정에 관한 것이다. 제안된 감마 수정 시스템은 일반적인 공식에 의해 만들어지는 비선형적 특성을 지닌 감마 커브와 제안된 알고리즘에 의해 생성되는 결과와 차이를 최소화하기 위한 시스템이다. 오차를 최소하기 위해, 제안된 시스템은 Least Squares Polynomial을 사용하였다. 이 알고리즘은 샘플간의 점들에 대해서 최적의 다항식을 계산하는 방법이다. 각각의 시스템들은 연속적인 여러 개의 방정식으로 구성되어 있으며, 정밀도를 높이기 위해서 각 구간마다 고유의 중첩 구간을 가지고 있다. 최종적으로 알고리즘을 검증하여, 시스템들은 Verilog-HDL를 사용하여 구현되었다. 본 논문에선 가장 초기적 알고리즘인, Seed Table을 이용한 기존 시스템과 이를 개선하기 위해 만들어진 제안된 감마 시스템을 비교하려고 한다. 제안된 시스템과 기존 시스템은 클럭 대기(clock latency)가 1과 2의 값을 지닌다. 그러나 에러 범위(LSB)는 $0{\sim}+36$에서 $-1{\sim}+1$으로 향상되었다. 삼성 0.35 worst case 환경에서 합성된 gate count는 2,063에서 2,564으로 증가되었으나, maximum data arrival time은 29.05[ns]에서 17.52[ns]으로 더 빨라졌다.

• 대한전기학회논문지:전기물성ㆍ응용부문C
• /
• 제51권3호
• /
• pp.134-140
• /
• 2002

Deep submicron NMOSFETs with elevated source/drain can be fabricated using self-aligned selective epitaxial growth(SEG) of silicon for enhanced device characteristics with shallow junction compared to conventional MOSFETs. Shallow junctions, especially with the heartily-doped S/D residing in the elevated layer, give hotter immunity to Yt roll off, drain-induced-barrier-lowering (DIBL), subthreshold swing (SS), punch-through, and hot carrier effects. In this paper, the characteristics of both deep submicron elevated source/drain NMOSFETs and conventional NMOSFETs were investigated by using TSUPREM-4 and MEDICI simulators, and then the results were compared. It was observed from the simulation results that deep submicron elevated S/D NMOSFETs having shallower junction depth resulted in reduced short channel effects, such as DIBL, SS, and hot carrier effects than conventional NMOSFETs. The saturation current, Idsat, of the elevated S/D NMOSFETs was higher than conventional NMOSFETs with identical device dimensions due to smaller sheet resistance in source/drain regions. However, the gate-to-drain capacitance increased in the elevated S/D MOSFETs compared with the conventional NMOSFETs because of increasing overlap area. Therefore, it is concluded that elevated S/D MOSFETs may result in better device characteristics including current drivability than conventional NMOSFETs, but there exists trade-off between device characteristics and fate-to-drain capacitance.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2009년도 추계학술대회 논문집
• /
• pp.5-5
• /
• 2009

Thin-film-transistors (TFTs) that can be prepared at low temperatures have attracted much attention because of the great potential for transparent and flexible electronics. One of the mainstreams in this field is the use of organic semiconductors such as pentacene. But device performance of the organic TFTs is still limited due to low field-effect mobility and rapid degradation after exposing to air. Alternative approach is the use of amorphous oxide semiconductors as a channel. Amorphous oxide semiconductors (AOSs) based TFTs showed the fast technological development, because AOS films can be fabricated at room temperature and exhibit the possibility in application like flexible display, electronic paper, and larges solar cells. Among the various AOSs, a-IGZO has lots of advantages because it has high channel mobility, uniform surface roughness and good transparency. [1] The high mobility is attributed to the overlap of spherical s-orbital of the heavy post-transition metal cations. This study demonstrated the effect of the variation in channel thickness from 30nm to 200nm on the TFT device performance. When the thickness was increased, turn-on voltage and subthreshold swing was decreased. The a-IGZO channels and source/drain metals were deposited with shadow mask. The a-IGZO channel layer was deposited on $SiO_2$/p-Si substrates by RF magnetron sputtering, where RF power is 150W. And working pressure is 3m Torr, at $O_2/Ar$ (2/28 sccm) atmosphere. The electrodes were formed with electron-beam evaporated Ti (30 nm) and Au (70 nm) bilayer. Finally, Al (150nm) as a gate metal was thermal-evaporated. TFT devices were heat-treated in a furnace at 250 $^{\circ}C$ and nitrogen atmosphere for 1hour. The electrical properties of the TFTs were measured using a probe-station. The TFT with channel thickness of 150nm exhibits a good subthreshold swing (SS) of 0.72 V/decade and on-off ratio of $1{\times}10^8$. The field effect mobility and threshold voltage were evaluated as 7.2 and 8 V, respectively.