• Transactions on Electrical and Electronic Materials
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• v.8 no.3
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• pp.139-142
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• 2007

Organic field-effect transistor (FET) based on a copper Phthalocyanine (CuPc) material as an active layer and a $SiO_2$ as a gate insulator were fabricated and analyzed. We measured the typical FET characteristics of CuPc in air. The electrical characteristics of the CuPc FET device were analyzed by a Maxwell-Wagner model. The Maxwell-Wagner model employed in analyzing double-layer dielectric system was helpful to explain the C-V and I-V characteristics of the FET device. In order to further clarity the channel formation of the CuPc FET, optical second harmonic generation (SHG) measurement was also employed. Interestingly, SHG modulation was not observed for the CuPc FET. This result indicates that the accumulation of charge from bulk CuPc makes a significant contribution.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.146-146
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• 2010

Electrical properties of Large-grain-size TIT with 7/7 ${\mu}m$ channel width and length which gate insulator is made of 20nm $SiO_2$ and 80nm $SiN_x$. was fabricated and measured with Large-grain-size technic(MICC) and compared to ELA technic's data. The field-effect mobility was decreased from 106.78 to $88.74\;cm^2$/Vs and threshold voltage also decreased from -1.8382 to -0.9529 V, when TFT process is changed from ELA technic to MICC technic. Subthreshold swing, also, increased from 0.22 to 0.32 V/dec and $I_{on/off}$ ratio decreased from $1.12{\times}10^8$ to $5.75{\times}10^7$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.149-149
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• 2008

Metal-Insulator-Metal(MIM) capacitors have been studied extensively for next generation of high-density dynamic random access memory (DRAM) devices. Of several candidates for metal electrodes, Ru or its conducting oxide $RuO_2$ is the most promising material due to process maturity, feasibility, and reliability. ALD can be used to form the Ru and RuO2 electrode because of its inherent ability to achieve high level of conformality and step coverage. Moreover, it enables precise control of film thickness at atomic dimensions as a result of self-limited surface reactions. Recently, ALD processes for Ru and $RuO_2$, including plasma-enhanced ALD, have been studied for various semiconductor applications, such as gate metal electrodes, Cu interconnections, and capacitor electrodes. We investigated Ru/$RuO_2$ thin films by thermal ALD with various deposition parameters such as deposition temperature, oxygen flow rate, and source pulse time. Ru and $RuO_2$ thin films were grown by ALD(Lucida D150, NCD Co.) using RuDi as precursor and O2 gas as a reactant at $200\sim350^{\circ}C$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.3
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• pp.158-166
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• 2001

Based on uniform hot carrier injection (optically assisted electron injection) across the $Si-SiO_2$ interface into the gate insulator of n-channel IGFETs, the threshold voltage shifts associated with electron injection of $1.25{\times}l0^{16}{\;}e/\textrm{cm}^2 between 0.5 and 7 MV/cm were found to decrease from positive to negative values, indicating both a decrease in trap cross section ($E_{ox}{\geq}1.5 MV/cm$) and the generation of FPC $E_{ox}{\geq}5{\;}MV/cm$). It was also found that FNC and large cross section NETs were generated for $E_{ox}{\geq}5{\;}MV/cm$. Continuous, uniform low-field (1MV/cm) electron injection up to $l0^{19}{\;}e/\textrm{cm}^2 is accompanied by a monatomic increase in threshold voltage. It was found that the data could be modeled more effectively by assuming that most of the threshold voltage shift could be ascribed to generated bulk defects which are generated and filled, or more likely, generated in a charged state. The injection method and conditions used in terms of injection fluence, injection density, and temperature, can have a dramatic impact on what is measured, and may have important implications on accelerated lifetime measurements.

• Journal of the Korean Institute of Telematics and Electronics
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• v.18 no.3
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• pp.25-34
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• 1981

Aluminum anodization method has been investigated for fabricating charge coupled device(CCD) with two-level aluminum gate structure. Al2O3 films were formed to a thickness of 400-500A, by anodizing aluminum with 30-35V of anode voltage for 2 hours using 2 % ammonium tartrate solution as an electrolyte. Breakdown voltage of these films were about 30 volts. Using above mentioned Al2O3 film as an insulator between two aluminum electrodes, CCD transversal low pass filter has been fabricated. CCD transversal low pass filter with 17 tap coefficients has shown 22 dB stop-band attenuation. The operating clock frequency range of the fabricated device was from 3 KHz to 100 KHz.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1988.05a
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• pp.78-81
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• 1988

Nitroxide films were made from the $NH_3$ gas nitridation of as-grown $SiO_2$. The electrical characterization results including C-V characteristics and BT stress generally indicate that the high field stress instability and insulator-substrate interfacial characteristics are improved by nitridation of $SiO_2$. A C-V technique was used to determine the surface state density $N_{55}$ and then $N_{55}$ in the nitroxide-substrate interface was $8{\times}10(/eVcm^2$). This $N_{55}$ is related with 1/f noise was revealed experimentally and relationship was plotted and 1/f noise characteristics were also improved by nitridation of of $SiO_2$By the results of measurements on these films show that very thin thermal silicon nitroxide films can be used as gate dielectrics for future highly scaled-down VLSI device.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.216-216
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• 2010

Floating gate를 이용한 플래시 메모리와 달리 질화막을 트랩 저장층으로 이용한 silicon-oxide-silicon nitride-oxide silicon (SONOS) 구조의 플래시 메모리 소자는 동작 전압이 낮고, 공정과정이 간단하며 비례 축소가 용이하여 고집적화하는데 유리하다. 그러나 SONOS 구조의 플래시 메모리소자는 비례 축소함에 따라 단 채널 효과와 펀치스루 현상이 커지는 문제점이 있다. 비례축소 할 때 발생하는 문제점을 해결하기 위해 플래시 메모리 소자를 FinFET과 같이 구조를 변화하는 연구는 활발히 진행되고 있으나, 플래시 메모리 소자를 제작하는 기판의 변화에 따른 메모리 소자의 전기적 특성 변화에 대한 연구는 많이 진행되지 않았다. 본 연구에서는 silicon-on insulator (SOI) 기판의 유무에 따른 멀티비트를 구현하기 위한 듀얼 게이트 가진 SONOS 구조를 가진 플래시 메모리 소자의 subthreshold 전압 영역에서의 전기적 특성 변화를 조사 하였다. 게이트 사이의 간격이 감소함에 따라 SOI 기판이 있을 때와 없을 때의 전류-전압 특성을 TCAD Simulation을 사용하여 계산하였다. 전류-전압 특성곡선에서 subthreshold swing을 계산하여 비교하므로 SONOS 구조의 플래시 메모리 소자에서 SOI 기판을 사용한 메모리 소자가 SOI 기판을 사용하지 않은 메모리 소자보다 단채널효과와 subthreshold swing이 감소하였다. 비례 축소에 따라 SOI 기판을 사용한 메모리 소자에서 단채널 효과와 subthreshold swing이 감소하는 비율이 증가하였다.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.08a
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• pp.264-264
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• 2011

1T-1C로 구성되는 기존의 dynamic random access memory (DRAM)는 데이터를 저장하기 위해 적절한 커패시턴스를 확보해야 한다. 따라서 커패시터 면적으로 인한 집적도의 한계에 직면해있으며, 이를 대체하기 위한 새로운 DRAM인 1T- DRAM이 연구되고 있다. 기존의 DRAM과 달리 silicon-on-insulator (SOI) 기술을 이용한 1T-DRAM은 데이터 저장을 위한 커패시터가 요구되지 않는다. 정공을 채널의 중성영역에 축적함으로서 발생하는 포텐셜 변화를 이용하며, 이때 발생하는 드레인 전류차를 이용하여 '0'과 '1'을 구분한다. 기존의 완전공핍형 평면구조의 1T-DRAM은 소스 및 드레인 접합부분에서 발생하는 누설전류로 인해 '0' 상태의 메모리 유지특성이 열화되는 단점을 가지고 있다. 따라서 메모리의 보존특성을 향상시키기 위해 소스/드레인 접합영역을 줄여 누설전류를 감소시키는 구조를 갖는 1T-DRAM의 연구가 필요하다. 또한 고유전율을 가지는 Si3N4를 이용한 oxide-nitride-oxide (ONO)구조의 게이트 절연막을 이용하면 동일한 두께에서 더 낮은 equivalent oxide thickness (EOT)를 얻을 수 있기 때문에 보다 저 전압에서 1T-DRAM 동작이 가능하여 기존의 SiO2 단일층을 이용한 1T-DRAM보다 동일 전압에서 더 큰 sensing margin을 확보할 수 있다. 본 연구에서는 누설전류를 감소시키기 위하여 소스 및 드레인이 채널위로 올려진 recessed channel 구조에 ONO 게이트 절연막을 적용한 1T-DRAM을 제작 및 평가하고, 본 구조의 1T-DRAM적용 가능성 및 ONO구조의 게이트 절연막을 이용한 sensing margin 개선을 확인하였다.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07a
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• pp.149-152
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• 2005

We present the characterization of poly-Si TFT fabricated below on Plastic Substrate below $170^{\circ}C$ on plastic substrate using excimer laser crystallization of Xe sputtered Si films. Gate insulator with a breakdown field exceeding 8 MV/cm was deposited by using inductively coupled plasma CVD. Finally, we successfully fabricate TFT with a electron field-effect mobility value greater than $290\;cm^2/Vsec$.

• Proceedings of the KIEE Conference
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• 1994.07b
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• pp.1463-1465
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• 1994

The electrical characteristics of $Al/Ta_2O_5/Si$ metal-oxide-semiconductor (MOS) capacitors were studied. $Ta_2O_5$ films on p-type silicon had been prepared by ionized cluster beam epitaxy technique (ICBE). This $Ta_2O_5$ films have low leakage current, high breakdown strength and low flat band shift. In this research, a single crystalline cpitaxial film of $Ta_2O_5$ has been grown on p-Si wafer using an ICBE technique. The native oxide layer ($SiO_2$) on the silicon substrate was removed below $500^{\circ}C$ by use of an accelerated arsenic ion beam, instead of a high temperature deposition. $Ta_2O_5$ films formed by ICBE technique can be received considerable attention for applications to coupling capacitors, gate dielectrics in MOS devices, and memory storage capacitor insulator because of their high dielectric constants above 20 and low temperature process.