• 제목/요약/키워드: Gate Dielectric Film

검색결과 253건 처리시간 0.028초

Plasma 처리한 유기 절연층을 갖는 유기 박막 트랜지스터의 전기적 특성 연구 (A Study on the Electrical Characteristics of Organic Thin Film Transistor, OTFT With Plasma-Treated Gate Insulators)

  • 김연주;박재훈;강성인;최종선
    • 한국진공학회지
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    • 제13권3호
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    • pp.99-102
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    • 2004
  • 유기 절연층을 사용한 유기 박막 트랜지스터의 특성 향상을 위해 절연층 표면에 Ar플라즈마 처리를 하였다. 플라즈마 처리는 절연체 표면의 화학적, 물리적 특성 변화를 통해 그 후에 이어지는 활성층 성막시 분자들의 결정성을 향상시키기 위한 방법이다. 활성층으로 사용된 물질은 pentacene이며, 절연층으로 사용된 물질은 PVP(poly-vinyl-phenol)이다. Pentacene는 약 $10^{-6}$ Torr에서 0.5 $\AA$/sec의 속도로, PVP는 spin coating법에 의해 각각 성막되었다. 형성된 절연층을 일정 시간동안 H플라즈마 처리 한 후 각 소자의 전기적 특성을 측정하여 표면처리에 의한 특성 변화를 살펴보았다.

Effect of the Hydrophobicity of Hybrid Gate Dielectrics on a ZnO Thin Film Transistor

  • Choi, Woon-Seop;Kim, Se-Hyun
    • Transactions on Electrical and Electronic Materials
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    • 제11권6호
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    • pp.257-260
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    • 2010
  • Zinc oxide (ZnO) bottom-contact thin-film transistors (TFTs) were prepared by the use of injector type atomic layer deposition. Two hybrid gate oxide systems of different polarity polymers with silicon oxide were examined with the aim of improving the properties of the transistors. The mobility and threshold voltage of a ZnO TFT with a poly(4-dimethylsilyl styrene) (Si-PS)/silicon oxide hybrid gate dielectric had values of 0.41 $cm^2/Vs$ and 24.4 V, and for polyimide/silicon oxide these values were 0.41 $cm^2/Vs$ and 24.4 V, respectively. The good hysteresis property was obtained with the dielectric of hydrophobicity. The solid output saturation behavior of ZnO TFTs was demonstrated with a $10^6$ on-off ratio.

Pentacene Thin-Film Transistors with Polyimide/$SiO_2$ Dual Gate Dielectric

  • Imahara, Hirokazu;Kim, Woo-Yeol;Oana, Yasuhisa;Majima, Yutaka
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권1호
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    • pp.972-973
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    • 2007
  • Relationships between field effect mobility and grain size on pentacene thin-film transistors with $polyimide/SiO_2$ gate dielectrics have been studied. 6 kinds of polyimide were used as surface treatment gate dielectric layer. Grain size of the pentacene thin film were between 5 and $30\;{\mu}m$ and depended on the polyimide. The field effect mobility were also depended on the polyimide and the those values were from 0.027 to $0.69\;cm^2/(Vs)$. The field effect mobility tends to increase with increasing the grain size. Precursor type polyimide containing polyamic acid show better mobility of $0.69\;cm^2/(Vs)$ than soluble type polyimide. Bias stress characteristics in air are discussed in the basis of the grain size.

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Sr-doped AlOx gate dielectrics enabling high-performance flexible transparent thin film transistors by sol-gel process

  • Kim, Jaeyoung;Choi, Seungbeom;Kim, Yong-Hoon
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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    • pp.301.2-301.2
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    • 2016
  • Metal-oxide thin-film transistors (TFTs) have gained a considerable interest in transparent electronics owing to their high optical transparency and outstanding electrical performance even in an amorphous state. Also, these metal-oxide materials can be solution-processed at a low temperature by using deep ultraviolet (DUV) induced photochemical activation allowing facile integration on flexible substrates [1]. In addition, high-dielectric constant (k) inorganic gate dielectrics are also of a great interest as a key element to lower the operating voltage and as well as the formation of coherent interface with the oxide semiconductors, which may lead to a considerable improvement in the TFT performance. In this study, we investigated the electrical properties of solution-processed high-k strontium-doped AlOx (Sr-AlOx) gate dielectrics. Using the Sr-AlOx as a gate dielectric, indium-gallium-zinc oxide (IGZO) TFTs were fabricated and their electrical properties are analyzed. We demonstrate IGZO TFTs with a 10-nm-thick Sr-AlOx gate dielectric which can be operated at a low voltage (~5 V).

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Photoacryl을 게이트 절연층으로 사용한 유기 박막 트랜지스터의 전기적 특성에 관한 연구 (A Study on the Electrical Characteristics of Organic Thin Film Transistor using Photoacryl as Gate Dielectric Layer)

  • 김윤명;표상우;심재훈;김영관;김정수
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2001년도 하계학술대회 논문집
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    • pp.247-250
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    • 2001
  • Organic semiconductors based on vacuum-deposited films of fused-ring polycyclic aromatic hydrocarbon have great potential to be utilized as an active layer for electronic and optoelectronic devices. We have fabricated organic thin film transistors(OTFTs) and discuss electrical characteristics of the devices. For the gate dielectric layer, OPTMER PC403 photoacryl(JSR Co.) was spin-coated and cured at 220$^{\circ}C$. Electrical characteristics of the device were investigated, where the photoacryl dielectric layer thickness and pentacene active layer thickness were about 0.6$\mu\textrm{m}$ and 800${\AA}$.

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Modification of Dielectric Surface in Organic Thin-Film Transistor with Organic Molecule

  • Kim, Jong-Moo;Lee, Joo-Won;Kim, Young-Min;Park, Jung-Soo;Kim, Jai-Kyeong;Ju, Byeong-Kwon;Oh, Myung-Hwan;Kim, Jong-Seung;Jang, Jin
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2004년도 Asia Display / IMID 04
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    • pp.1030-1033
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    • 2004
  • We herewith report for the effect of dielectric surface modification on the electrical characteristics of organic thin-film transistors (OTFTs). The kist-jm-1 as an organic molecule for the surface modification is deposited onto the surface of zirconium oxide ($ZrO_2$) gate dielectric layer. The OTFTs are elaborated on the flexible plastic substrates through 4-level mask process to yield a simple fabrication process. In this work, we also have examined the dependence of electrical performance on the interface surface state of gate dielectric/pentacene, which may be modified by chemical properties in the gate dielectric surface.

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Condensation and Baking Effects of Polymer Gate Insulator for Organic Thin Film Transistor

  • Kang, S.I.;Park, J.H.;Jang, S.P.;Choi, Jong-S.
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2004년도 Asia Display / IMID 04
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    • pp.1046-1048
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    • 2004
  • Performances of organic thin film transistors (OTFTs) can be detrimentally affected by the state of the gate dielectric. Because of the bad stability of polymers, OTFTs with polymer gate dielectrics often provide abnormal characteristics. In this study, we report the condensation effect of the polymer gate dielectric layer. For the observations of the effect of the condensation, the spin-coated polymer layers with various deposition conditions were fabricated and left under low vacuum condition for several days. It is observed that the thickness of polymer layer and the electrical characteristic of OTFTs vary with the condensation time.

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Routes to Improving Performance of Solution-Processed Organic Thin Film Transistors

  • Li, Flora M.;Hsieh, Gen-Wen;Nathan, Arokia;Beecher, Paul;Wu, Yiliang;Ong, Beng S.;Milne, William I.
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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    • pp.1051-1054
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    • 2009
  • This paper investigates approaches for improving effective mobility of organic thin film transistors (OTFTs). We consider gate dielectric optimization, whereby we demonstrated >2x increase in mobility by using a silicon-rich silicon nitride ($SiN_x$) gate dielectric for polythiophene-based (PQT) OTFTs. We also engineer the dielectric-semiconductor ($SiN_x$-PQT) interface to attain a 27x increase in mobility (up to 0.22 $cm^2$/V-s) using an optimized combination of oxygen plasma and OTS SAM treatments. Augmentative material systems by combining 1-D nanomaterials (e.g., carbon nanotubes, zinc oxide nanowires) in an organic matrix for nanocomposite OTFTs provided a further boost in device performance.

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Bias stress effect in organic thin-film transistors with cross-linked PVA gate dielectric and its reduction method using $SiO_2$ blocking layer

  • Park, Dong-Wook;Lee, Cheon-An;Jung, Keum-Dong
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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    • pp.445-448
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    • 2006
  • Bias stress effect in pentacene organic thin-flim transistors with cross-linked PVA gate dielectric is analyzed. For negative gate bias stress, positive threshold voltage shift is observed. The injected charges from the gate electrode to the defect states of gate dielectric are regarded as the main origin of $V_T$ shift. The reduced bias stress effect using $SiO_2$ blocking layer confirms the assumed mechanism. It is also demonstrated that the inverter with $SiO_2$ blocking layer shows the negligible hysteresis owing to the reduced bias stress effect.

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