• 대한전자공학회논문지TC
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• 제42권3호
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• pp.1-8
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• 2005

본 논문에서는 3GPP 중계기 및 기지국용 60W급 Doherty 전력증폭기를 설계 및 제작하였다. Doherty 전력증폭기는 효율개선과 고출력 특성이 뛰어나지만 보조증폭기의 구현이 어렵다. 이를 해결하고자 일반적인 Doherty 전력증폭기에 보조증폭기의 Gate 바이어스 조절회로를 첨가한 GCHD(Gate Control Hybrid Doherty) 전력증폭기를 구현하였다. 실험결과 3GPP 동작주파수 대역인 $2.11\~2.17GHz$에서 이득이 62.55 dB이고, PEP 출력이 50.76 dBm, W-CDMA 평균전력 47.81 dBm, 5MHz offset 주파수대역에서 -40.05 dBc의 ACLR 특성을 가졌으며, 각각의 파라미터는 설계하고자 하는 증폭기의 사양을 만족하였다. 특히 GCHD 전력증폭기는 일반전력증폭기에 비해 ACLR에 따른 효율 개선성능이 우수하였다.

• 전자공학회논문지C
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• 제36C권1호
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• pp.59-65
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• 1999

MPEG-II 기반의 HDTV/DTV Encoder 구성부중 하나인 엔트로피 부호화기(entropy encoder)를 설계하였다. 설계된 엔트로피 부호화기는 생성된 비트스트림이 버퍼에 저장될 경우 버퍼의 고갈을 막기위해 제로 스터핑 블록을 첨가함으로써 9Mbps의 비트율로 출력된다. 또한, AC 계수와 DC 계수 table로 PROM이 아닌 조합회로를 사용하여 회로내부에 Critical path가 발생하지 않도록 하였다. 패커부의 경우 배럴 쉬프트 하나를 사용하여 24비트 단위로 패킹을 하도록 하였으며, 헤더정보 부호화부, 입력정보지연부, 부호화부 그리고 버퍼 제어부로 구성된다. 설계된 회로는 VHDL function 시뮬레이션을 통하여 검증하였고, 설계공정 파라미터로는 $0.8{\mu}m$ Gate Array 설계방식을 적용하여 Gate compiler로 P&R을 수행한 결과 전체 Layout의 핀 수와 Gate수는 각각 235개와 120,000개로 측정되었다.

• 한국실내디자인학회논문집
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• 제20권4호
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• pp.74-82
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• 2011

All the phenomena and subjects of nature and society are within correlation interconnection, and they are inseparably connected one another. The elements of this interaction can be found out through the concept of transparency in the space composition of Korean traditional architecture. This study is focusing on the access space, in other words, a gate-house that is a buffer zone playing a process role up to the main space among successive spaces. It was chosen to be the subject of the study since it strengthens convergence into the main building and with the effect connecting spaces, it could show well the spatial possibility of transparency. Besides, the subject of the study is limited to the Moonru Multi roofs that improves the functionality of spaces between gate-houses, and it is intended to progress contents by comparative analysis of two kinds such as Seo Won gate-house and temple gate-house. Korean traditional architecture places emphasis on harmony within the whole spaces. There are intimate relations between surrounding environment, external spaces and internal spaces, and it is important understand the spatial relations according to the shape appearing through interactions of parts in the whole spaces. In conclusion, the Moonru Multi roofs is analyzed with the method of extracting the concept that is contained in the frame of analysis and through ecological views through a visible and structural method. It can be understood what kinds of method for communication were used for ancestors to recognize and use spaces with the deduced concept through the analysis of the Moonru Multi roofs with different character.

• 전자공학회논문지A
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• 제30A권2호
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• pp.76-85
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• 1993

This paper describes the design of a technology-independent logic, function, and timing extraction system from SPICE-like network descriptions. Technology-independent extraction mechanism is provided in the form of technology files containing the rules for constructing logic gates and functional blocks. The designed system can be more effectively used in cell-based design by describing the cells to be extracted. Timing extraction is performed by using a linear RC gate delay model which takes interconnection delay into account. Experimental results show that estimated delay is within 10 percents for logic gate circuits when compared with SPICE. Through higher-level design descriptions obtained by extraction, design cycles can be considerably reduces.

• 한국기계가공학회지
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• 제7권1호
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• pp.38-46
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• 2008

Design technology and speciality production technology to manufacture high quality valve are insufficient in Korea. In order to design the experiments using Taguchi method and Variational Technology Also, from verification of the response model with optimized results was confirmed that usefulness and reliance of application Taguchi method and Variational Technology to structural's optimum design using Taguchi method and Variational Technology.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.1096-1099
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• 2001

The basic design structure of RC-GCTs (Reserve-Conducting Gate-Commutated Thyristors) is firstly given in this paper. The bulk of wafer is punch-through (PT) type with high resistivity and narrow N-base width. The photo-mask was designed upon the turn-off characteristics of GCT and solution of separation between GCT and diode part. The center part of Si wafer is free-wheeling diode (FWD) and outer is GCT part which has 240 fingers totally. The switching performance of GCT was investigated by Dessis of ISE. The basic manufacture process of 2500V-4500V RC-GCTs was given in this work. Additionally, the local carrier lifetime control by 5Mev proton irradiation was adopted so as to not only to have the softness of reverse recovering for FWD but for reduction of turn-off losses of GCT as well.

• 한국실내디자인학회논문집
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• 제17권5호
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• pp.72-79
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• 2008

Nagaya is one of the traditional Japanese housing types in which multiple houses are attached together. In Nagaya, walls are shared by several houses but entrances are privately owned by houses. Nagaya consists of many wooden houses for common people located in parallel with narrow alleys between them. Nagaya was one of the representative housing types in Japanese architectural history. This research is to study the background of the origination of Nagaya in Japan, the characteristics of space and land planning, the features and causes of the changes in the space and land planning. In this research, we observed and analyzed unit plans of a block of gate-type Nagayas in Hanan, Osaka. The results are as follows. First, as the inner alleys(Roji) are closed, the number of entrances to each housing lot decreased from two to one since one entrance that used to be open to inner alleys(Roji) are permanently closed. Second, walls between streets and housing lots which used to be one of the outstanding characteristics of gate-type Nagayas are disappearing. Third, as the bathrooms are added to houses, the front gardens are being degraded to empty spaces or sometimes totally removed. Fourth, the space in the first floor of houses become family spaces, and that in the second floor is divided into private rooms for individuals.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2012년도 추계학술대회
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• pp.835-837
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• 2012

본 연구에서는 상단게이트와 하단게이트를 갖는 (Double gate ; DG) MOSFET 구조의 소자 파라미터에 따른 전도중심을 분석하였다. 분석학적 모델을 유도하기 위하여 포아송 방정식을 이용하였다. 본 연구에서 제시한 모델을 사용하여 DGMOSFET 설계시 중요한 채널길이, 채널두께, 그리고 게이트 산화막 두께 등의 요소 변화에 대한 전도중심의 변화를 관찰하였다. 또한 채널 도핑농도에 따른 전도중심의 변화를 고찰함으로써 DGMOSFET의 타당한 채널도핑농도를 결정하였다.

• 전자공학회논문지SC
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• 제47권1호
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• pp.29-34
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• 2010

본 논문에서는 새로운 패리티 보존형 가역 논리게이트를 제안한다. 패리티 보존형 가역 논리게이트는 입력 값과 출력 값의 패리티가 같은 가역 논리게이트를 의미한다. 최근 가역 논리 게이트가 저전력 CMOS 디자인, 양자 컴퓨팅 그리고 나노 테크놀로지와 같은 분야에서 전력을 효율적으로 사용하는 방법임을 알려졌다. 그리고 패리티 체크(parity-checking)는 디지털 시스템에서 오류 주입을 확인 하는 대표적인 방법 중 하나이다. 제안하는 새로운 패리티 보존형 가역 논리게이트는 모든 boolean 함수를 구성할 수 있고, 기존의 오류 확인 boolean 함수보다 가역 논리게이트 수, garbage-output의 수 그리고 하드웨어 연산량에서 효율적으로 구성할 수 있다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 하계학술대회 논문집 Vol.5 No.1
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• pp.280-283
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• 2004

This paper discribes the design concept, fabrication process and measuring result of 2.5kV Gate Commutated Thyristor devices. Integrated gate commutated thyristors(IGCTs) is the new power semiconductor device used for high power inverter, converter, static var compensator(SVC) etc. Most of the ordinary GTOs(gate turn-off thyristors) are designed as non-punch-through(NPT) concept; i.e. the electric field is reduced to zero within the N-base region. In this paper, we propose transparent anode structure for fast turn-off characteristics. And also, to reach high breakdown voltage, we used 2-stage bevel structure. Bevel angle is very important for high power devices, such as thyristor structure devices. For cathode topology, we designed 430 cathode fingers. Each finger has designed $200{\mu}m$ width and $2600{\mu}m$ length. The breakdown voltage between cathode and anode contact of this fabricated GCT device is 2,715V.