• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.2
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• pp.15-21
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• 2008

This paper discuss the sequential digital logic systems and arithmetic operation algorithms which is the important material in computer architecture using analysis and synthesis which is based on extension logic for binary logic over galois fields. In sequential digital logic systems, we construct the moore model without feedback sequential logic systems after we obtain the next state function and output function using building block T-gate. Also, we obtain each algorithms of the addition, subtraction, multiplication, division based on the finite fields mathematical properties. Especially, in case of P=2 over GF($P^m$), the proposed algorithm have a advantage which will be able to apply traditional binary logic directly.The proposed method can construct more efficiency digital logic systems because it can be extended traditional binary logic to extension logic.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.6
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• pp.17-28
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• 2002

XTR is a new method to represent elements of a subgroup of a multiplicative group of a finite field GF( $p^{6m}$) and it can be generalized to the field GF( $p^{6m}$)$^{[6,9]}$ This paper progress optimal extention fields for XTR among Galois fields GF ( $p^{6m}$) which can be aplied to XTR. In order to select such fields, we introduce a new notion of Generalized Opitimal Extention Fields(GOEFs) and suggest a condition of prime p, a defining polynomial of GF( $p^{2m}$) and a fast method of multiplication in GF( $p^{2m}$) to achieve fast finite field arithmetic in GF( $p^{2m}$). From our implementation results, GF( $p^{36}$ )longrightarrowGF( $p^{12}$ ) is the most efficient extension fields for XTR and computing Tr( $g^{n}$ ) given Tr(g) in GF( $p^{12}$ ) is on average more than twice faster than that of the XTR system on Pentium III/700MHz which has 32-bit architecture.$^{［6,10］/ ［6,10］/6,10］}$

• Journal of the Institute of Convergence Signal Processing
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• v.2 no.3
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• pp.102-109
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• 2001

In this paper, a new multiplication algorithm which describes the methods of constructing a multiplierover GF(p$^{m}$ ) was presented. For the multiplication of two elements in the finite field, the multiplication formula was derived. Multiplier structures which can be constructed by this formula were considered as well. For example, both GF(3) multiplication module and GF(3) addition module were realized by current-mode CMOS technology. By using these operation modules the basic cell used in GF(3$^{m}$ ) multiplier was realized and verified by SPICE simulation tool. Proposed multipliers consisted of regular interconnection of simple cells use regular cellular arrays. So they are simply expansible for the multiplication of two elements in the finite field increasing the degree m.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.9 no.2
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• pp.714-727
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• 2015

The hierarchical structure in networks is widely applied in many practical scenarios especially in some emergency cases. In this paper, we focus on a tree network with and without packet loss where one source sends data to n destinations, through m relay nodes employing random linear network coding (RLNC) over a Galois field in parallel transmission systems. We derive closed-form probability expressions of successful decoding at a destination node and at all destination nodes in this multicast scenario. For the convenience of computing, we also propose an upper bound for the failure probability. We then investigate the impact of the major parameters, i.e., the size of finite fields, the number of internal nodes, the number of sink nodes and the channel failure probability, on the decoding performance with simulation results. In addition, numerical results show that, under a fixed exact decoding probability, the required field size can be minimized. When failure decoding probabilities are given, the operation is simple and its complexity is low in a small finite field.

• The Journal of Society for e-Business Studies
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• v.11 no.2
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• pp.1-11
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• 2006

This paper proposes an efficient inversion algorithm for Galois field GF(2n) by using a modified multi-bit shifting method based on the Montgomery algorithm. It is well known that the efficiency of arithmetic algorithms depends on the basis and many foregoing papers use either polynomial or optimal normal basis. An inversion algorithm, which modifies a multi-bit shifting based on the Montgomery algorithm, is studied. Trinomials and AOPs (all-one polynomials) are tested to calculate the inverse. It is shown that the suggested inversion algorithm reduces the computation time up to 26 % of the forgoing multi-bit shifting algorithm. The modified algorithm can be applied in various applications and is easy to implement.

• Journal of Communications and Networks
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• v.16 no.3
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• pp.270-279
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• 2014

The Viterbi decoding algorithm, which provides maximum - likelihood decoding, is currently considered the most widely used technique for the decoding of codes having a state description, including the class of linear error-correcting convolutional codes. Two classes of nonbinary convolutional codes are presented. Distance preserving mapping convolutional codes and M-ary convolutional codes are designed, respectively, from the distance-preserving mappings technique and the implementation of the conventional convolutional codes in Galois fields of order higher than two. We also investigated the performance of these codes when combined with a multiple frequency-shift keying (M-FSK) modulation scheme to correct narrowband interference (NBI) in power-line communications channel. Themodification of certain detectors of the M-FSK demodulator to refine the selection and the detection at the decoder is also presented. M-FSK detectors used in our simulations are discussed, and their chosen values are justified. Interesting and promising obtained results have shown a very strong link between the designed codes and the selected detector for M-FSK modulation. An important improvement in gain for certain values of the modified detectors was also observed. The paper also shows that the newly designed codes outperform the conventional convolutional codes in a NBI environment.

• Journal of the Korean Institute of Telematics and Electronics
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• v.17 no.2
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• pp.29-36
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• 1980

This paper presents a method for constructing multiple- valued switching functions based on Galois fields. First the constructing Inethod for single- variable switching functions is developers and the results are extended to multiple- variable functions. The fundalnental Inathelnatical properties used in this paper are. (1) The sum of all elements over CF of is zero. (2) The Product of nonzero elements over GF(N) is equal to e1 for Neven, and e1( ) for N odd. With these properties, a relatlvely simple constructing method is developed, and a process for determining the coefficients of the expanded forms of switching functions is also obtained without successive multiplication of the polynomials. Some examples are given to illustrate the method.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.9 no.1
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• pp.89-94
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• 2009

This paper proposes the algorithms that design the highly digital logic circuit and assign the code to each node of DCG(Directed Cyclic Graph) of length ${\zeta}$. The conventional algorithm have some problems, so this paper introduce the matrix equation from DCG of length ${\zeta}$ and proposes highly digital logic circuit design algorithms according to the DCG of length ${\zeta}$. Using the proposed circuit design algorithms in this paper, it become realized that was able to design from former algorithm. Also, making a comparison between the circuit using former algorithm and this paper's, we testify that proposed paper's algorithm is able to realize more optimized circuit design. According to proposed circuit design algorithm in this paper, it is possible to design current that DCG have natural number, so it have the following advantages, reduction of the circuit input/output digits, simplification of circuit composition, reduction of computation time and cost. And we show comparability and verification about this paper's algorithm.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.13 no.2
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• pp.127-132
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• 2003

Cryptosystems have received very much attention in recent years as importance of information security is increased. Most of Cryptosystems are defined over finite or Galois fields GF($2^m$) . In particular, the finite field GF($2^m$) is mainly used in public-key cryptosystems. These cryptosystems are constructed over finite field arithmetics, such as addition, subtraction, multiplication, and multiplicative inversion defined over GF($2^m$) . Hence, to implement these cryptosystems efficiently, it is important to carry out these operations defined over GF($2^m$) fast. Among these operations, since multiplicative inversion is much more time-consuming than other operations, it has become the object of lots of investigation. Recently, many methods for computing multiplicative inverses at hi호 speed has been proposed. These methods are based on format's theorem, and reduce the number of required multiplication using normal bases over GF($2^m$) . The method proposed by Itoh and Tsujii[2] among these methods reduced the required number of times of multiplication to O( log m) Also, some methods which improved the Itoh and Tsujii's method were proposed, but these methods have some problems such as complicated decomposition processes. In practical applications, m is frequently selected as a power of 2. In this parer, we propose a fast method for computing multiplicative inverses in GF($2^m$) , where m = ($2^n$) . Our method requires fewer ultiplications than the Itoh and Tsujii's method, and the decomposition process is simpler than other proposed methods.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.17 no.1
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• pp.33-39
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• 2007

Finite field multipliers are the basic building blocks in many applications such as error-control coding, cryptography and digital signal processing. Hence, the design of efficient dedicated finite field multiplier architectures can lead to dramatic improvement on the overall system performance. In this paper, a new bit serial structure for a multiplier with low latency in Galois field is presented. To speed up multiplication processing, we divide the product polynomial into several parts and then process them in parallel. The proposed multiplier operates standard basis of $GF(2^m)$ and is faster than bit serial ones but with lower area complexity than bit parallel ones. The most significant feature of the proposed architecture is that a trade-off between hardware complexity and delay time can be achieved.