• Proceedings of the Korea Information Processing Society Conference
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• 2021.11a
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• pp.446-448
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• 2021

In training a deep learning model, it is crucial to tune various hyperparameters and gain speed and accuracy. While hyperparameters that mathematically induce convergence impact training speed, system parameters that affect host-to-device transfer are also crucial. Therefore, it is important to properly tune and select parameters that influence the data loader as a system parameter in overall time acceleration. We propose an automated framework called Num Worker Tuner (NWT) to address this problem. This method finds the appropriate number of multi-processing subprocesses through the search space and accelerates the learning through the number of subprocesses. Furthermore, this method allows memory efficiency and speed-up by tuning the system-dependent parameter, the number of multi-process spawns.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.14 no.7
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• pp.3425-3430
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• 2013

The fast-growing market in wireless communications has led to the development of multi-standard mobile terminals. In this paper, a frequency-tunable active RC bandpass filter for multi-standards wireless communication system is designed using an active inductor. The conventional bandpass filter design methods employ the high order filter or high quality factor Q to improve the stopband attenuation characteristics and frequency selectivity of the passband. The proposed bandpass filter based on the high Q active inductor has an improved frequency characteristics. The center frequency and gain of the designed bandpass filter is tuned by employing the tuning circuit. We have performed the simulation using TSMC $0.18{\mu}m$ process parameter to analyze the characteristics of the designed active RC bandpass filter. The bandpass filter with Q=20.5 has 90MHz half power bandwidth at the center frequency of 1.86GHz. Moreover, the center frequency of the proposed bandpass filter can be tuned between 1.86~2.38GHz for the multi-standards wireless communication system using the capacitor of the tuning circuit.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.11
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• pp.48-56
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• 2011

Novel class-A bipolar current conveyor($CCII{\pm}$) with differential current output and its application to output current controllable CCII+ for electronic tuning systems are designed. The $CCII{\pm}$ is consists of conventional CCII+ and complementary cross current sources. The CCII+ with controllable the output current consists of the $CCII{\pm}$ and a current gain amplifier with single-ended current output. The simulation result shows that the $CCII{\pm}$ has current input impedance of $1.9{\Omega}$ and a good linearity for voltage and current follower. The proposed CCII+ has 3-dB cutoff frequency of 10MHz for the range over bias control current $100{\mu}A$ to 10mA. The range of output current control is four decade. The power dissipation of the CCII+ is 4.5mW at supply voltage of ${\pm}2.5V$.

• Korean Journal of Optics and Photonics
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• v.13 no.1
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• pp.15-20
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• 2002

We demonstrate a widely-tunable wavelength converter based on four-wave mixing in a semiconductor-fiber ring laser with no external pump light. Applying 10 GHz short pulses at -8 dBm as a probe signal, we achieve continuous wavelength tuning over the semiconductor optical amplifier gain-bandwidth reaching 30 nm down- and 17 m up-wavelength conversion. In addition to the wide tuning capability, the converter shows high-speed conversion and low saturation power capabilities.

• Journal of Institute of Control, Robotics and Systems
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• v.10 no.10
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• pp.855-868
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• 2004

There are several types of singularities in controlling robotic manipulators: kinematic singularity, algorithmic singularity, semi-kinematic singularity, semi-algorithmic singularity, and representation singularity. The kinematic and algorithmic singularities have been investigated intensively because they are not predictable or difficult to avoid. The problem with these singularities is an unnecessary performance reduction in non-singular region and the difficulty in performance tuning. Tn this paper, we propose a method of avoiding kinematic and algorithmic singularities by applying a task reconstruction approach while maximizing the task performance by calculating singularity measures. The proposed method is implemented by removing the component approaching the singularity calculated by using singularity measure in real time. The outstanding feature of the proposed task reconstruction method (TR-method) is that it is based on a local task reconstruction as opposed to the local joint reconstruction of many other approaches. And, this method has dynamic task priority assignment feature which ensures the system stability under singular regions owing to the change of task priority. The TR-method enables us to increase the task controller gain to improve the task performance whereas this increase can destabilize the system for the conventional algorithms in real experiments. In addition, the physical meaning of tuning parameters is very straightforward. Hence, we can maximize task performance even near the singular region while simultaneously obtaining the singularity-free motion. The advantage of the proposed method is experimentally tested by using the 7-dof spatial manipulator, and the result shows that the new method improves the performance several times over the existing algorithms.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.2
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• pp.73-78
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• 2011

A frequency synthesizer for DAB applications is designed using $0.18{\mu}m$ CMOS process with 1.8V supply. NP-core type is chosen for VCO core to improve low power characteristic and symmetric characteristic of output waveform. VCO range is 1302.34 MHz - 1949.51 MHz using switchable capacitor bank and varactor bank. Varactor biases that improve varactor capacitance characteristics were minimized as two, $K_{vco}$(VCO gain) is maintained using technique of varactor bank switching. Intervals of $K_{vco}$ are maintained adding VCO frequency compensation logic. Each block of VCO and frequency synthesizer designed $0.18{\mu}m$ CMOS process with 1.8V supply is verified by Cadence Spectre, measured VCO consumes 9mA current, and is 39.8% tuning range, total power consumption of the frequency synthesizer is 18mW.

• Journal of Power Electronics
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• v.11 no.3
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• pp.360-368
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• 2011

This paper proposes an active frequency with a positive feedback in the d-q frame anti-islanding method suitable for a robust phase-locked loop (PLL) algorithm using the FFT concept. In general, PLL algorithms for grid-connected PV PCS use d-q transformation and controllers to make zero an imaginary part of the transformed voltage vector. In a real grid system, the grid voltage is not ideal. It may be unbalanced, noisy and have many harmonics. For these reasons, the d-q transformed components do not have a pure DC component. The controller tuning of a PLL algorithm is difficult. The proposed PLL algorithm using the FFT concept can use the strong noise cancelation characteristics of a FFT algorithm without a PI controller. Therefore, the proposed PLL algorithm has no gain-tuning of a PI controller, and it is hardly influenced by voltage drops, phase step changes and harmonics. Islanding prediction is a necessary feature of inverter-based photovoltaic (PV) systems in order to meet the stringent standard requirements for interconnection with an electrical grid. Both passive and active anti-islanding methods exist. Typically, active methods modify a given parameter, which also affects the shape and quality of the grid injected current. In this paper, the active anti-islanding algorithm for a grid-connected PV PCS uses positive feedback control in the d-q frame. The proposed PLL and anti-islanding algorithm are implemented for a 250kW PV PCS. This system has four DC/DC converters each with a 25kW power rating. This is only one-third of the total system power. The experimental results show that the proposed PLL, anti-islanding method and topology demonstrate good performance in a 250kW PV PCS.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.40-49
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• 2008

A Frequency synthesizer for mobile-DTV applications is implemented using $0.18{\mu}m$ CMOS process with 1.8V supply. PMOS transistors are chosen for VCO core to reduce phase noise. The measurement result of VCO frequency range is 800MHz-1.67GHz using switchable inductors, capacitors and varactors. We use varactor bias technique for the improvement of VCO gain linearity, and the number of varactor biasing are minimized as two. VCO gain deterioration is also improved by using the varactor switching technique. The VCO gain and interval of VCO gain are maintained as low and improved using the VCO frequency calibration block. The sigma-delta modulator for fractional divider is designed by the co-simualtion method for accuracy and efficiency improvement. The VCO, PFD, CP and LF are verified by Cadence Spectre, and the sigma-delta modulator is simulated using Matlab Simulink, ModelSim and HSPICE. The power consumption of the frequency synthesizer is 18mW, and the VCO has 52.1% tuning range according to the VCO maximum output frequency. The VCO phase noise is lower than -100dBc/Hz at 1MHz at 1MHz offset for 1GHz, 1.5GHz, and 2GHz output frequencies.

• The Journal of the Korea institute of electronic communication sciences
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• v.4 no.3
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• pp.183-189
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• 2009

In this paper, we propose RF front-end architecture using hybrid conversion method to receive broadband signal. The validity is verified by design, fabrication and experiment. The proposed RF front-end architecture due to up-conversion block improves the deficiency of performance deterioration to be generated through harmonic signal and image signal conversion in the conventional RF front-end, and improves the deficiency of the complexity that is from to adopt a multiple local oscillators for the generation of wideband LO signal in the conventional RF front-end by applying the principle that tuning bandwidth is multiplied at sub-harmonic mixer. Manufactured circuits satisfy the deduced design specification and target standard with gain above 80 dB, noise figure below 6.0 dB and IIP3 performance above -5.0 dBm for the condition of the minimum gain in RF front-end.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.12
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• pp.3638-3644
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• 2009

A CMOS multi-channel low-voltage current mode filter circuit is designed. The designed current-mode filter is based on linear cascode current-mode integrator that is newly proposed in this paper. When it is compared with that of the typical current-mirror type current-mode integrator, the proposed linear cascode current-mode integrator achieves high current gain and unity gain frequency. The designed filter is composed with 5th Chebyshev function and converted to active version by signal flow graph method. We verified that the designed filter can be applied to three-channel basedband, bluetooth, DECT and WCDMA with 0.51MHz~7.03MHz frequency tuning range by Hspice simulation using 1.8V-$0.18{\mu}m$ CMOS technology.