• IEIE Transactions on Smart Processing and Computing
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• 제6권2호
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• pp.133-139
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• 2017

Vehicles have increasingly evolved and become intelligent with convergence of information and communications technologies (ICT). Vehicle communications (VC) has become one of the major necessities for intelligent vehicles. However, VC suffers from serious security problems that hinder its commercialization. Hence, the IEEE 1609 Wireless Access Vehicular Environment (WAVE) protocol defines a security service for VC. This service includes Advanced Encryption Standard-Counter with CBC-MAC (AES-CCM) for data encryption in VC. A high-speed AES-CCM crypto module is necessary, because VC requires a fast communication rate between vehicles. In this study, we propose and implement an efficient AES-CCM hardware architecture for high-speed VC. First, we propose a 32-bit substitution table (S_Box) to reduce the AES module latency. Second, we employ key box register files to save key expansion results. Third, we save the input and processed data to internal register files for secure encryption and to secure data from external attacks. Finally, we design a parallel architecture for both cipher block chaining message authentication code (CBC-MAC) and the counter module in AES-CCM to improve performance. For implementation of the field programmable gate array (FPGA) hardware, we use a Xilinx Virtex-5 FPGA chip. The entire operation of the AES-CCM module is validated by timing simulations in Xilinx ISE at a speed of 166.2 MHz.

• 대한전기학회논문지:전력기술부문A
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• 제48권12호
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• pp.1554-1563
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• 1999

This paper presents the design of high speed processor for a sequence logic control using field programmable gate array(FPGA). The sequence logic controller is widely used for automating a variety of industrial plants. The FPGA designed by VHDL consists of program and data memory interface block, input and output block, instruction fetch and decoder block, register and ALU block, program counter block, debug control block respectively. Dedicated clock inputs in the FPGA were used for high speed execution, and also the program memory was separated from the data memory for high speed execution of the sequence instructions at 40 MHz clock. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 16 bits or 32 bits respectively. And the real time debug operation was implemented for easy debugging the designed processor. This FPGA was synthesized by pASIC 2 SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to sequence control system with inputs and outputs of 256 points. The designed processor for the sequence logic was compared with the control system using the DSP(TM320C32-40MHz) and conventional PLC system. The designed processor for the sequence logic showed good performance.

• 정보처리학회논문지A
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• 제12A권1호
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• pp.1-6
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• 2005

본 논문에서는 trace-back systolic array Viterbi algorithm의 저전력 생존 메모리 구현에 관한 새로운 알고리즘을 소개한다. 이 알고리즘의 핵심 아이디어는 trace back 연산의 수를 줄이기 위하여 이미 생성된 trace-back routes를 재사용하는 것이다. 그리고 trace-back unit의 불필요한 switching activity가 발생하는 영역을 gate-clock을 사용하여 전력소모를 줄이는 것이다. Synopsys Power Estimation 툴인 Design Power를 이용하여 전력소모를 측정하였고, 그 결과 [1]의 논문에서 소개된 trace-back unit 비하여 평균 $40{\%}$ 전력감소가 있었고, $23{\%}$의 면적증가를 보였다.

• 교육시설
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• 제11권4호
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• pp.15-24
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• 2004

The purpose of this study is to suggest some alternative on site planning of elementary school through investigating the effects of geographical and urban environment on the site. For this, we selected and surveyed 35 schools in Gwangju. The results of this study are as follows. 1) We cannot find out the differences from the use of elementary schools sites on slopes of sites. However, the sunken space between H type buildings in the site slopes facing east or west and the placing the playground on the north side of the site slopes facing north have some problems 2) The number of adjacent road and surrounding environment didn't show any effect. To separate between cars and pedestrians, we need some plans to block cars on the pedestrian gateway and it is much better to intensify the parking area near the school gate that cars come in and out. 3) The degree of satisfaction on the outdoor facilities of these cases shows low level. Therefore, to use the site of schools efficiently, we should secure the spacious playground and make plans to provide some spaces around school building for the static activities of students and teachers. 4) Most of all, the site which is suitable for educational environment should be selected. and also Special Code on the urban plan should be established to develop this one.

• 한국항공우주학회지
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• 제32권7호
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• pp.83-90
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• 2004

본 논문은 중, 대형 비행체에 분산 탑재되어 있는 많은 센서를 효과적으로 실시간 데이터를 수집할 수 있는 시스템의 구성도를 소개하고 각종 서브 장치의 회로, 장치들간의 통신 프로토콜에 대한 설계 내용 그리고 최종적으로 실험을 통해 성능 검증한 내용을 언급한다. 각 장치들은 FPGA 소자를 기본으로 하여 모든 제어 로직, 시퀀스 로직 등의 디지털 회로를 설계 및 시뮬레이션을 수행하였으며 그 결과를 바탕으로 실제 하드웨어를 제작하여 원거리 아날로그 및 디지털 데이터의 획득, 수집 및 포맷의 일련의 과정들이 정상 적으로 이루어지는지를 확인하였다.

• 한국유체기계학회 논문집
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• 제2권1호
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• pp.7-14
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• 1999

This simulation method is developed by using GateCycle code for the performance evaluation of the gas turbine in IGCC(Integrated Gasification Combined Cycle) power plant that uses clean coal gas fuel derived from coal gasification and gas clean-up processes and it is integrated with ASU(Air Separation Unit). In the present simulation method, thermodynamic calculation procedure is incorporated with compressor performance map and expander choking models for considering the off-design effects due to coal gas firing and ASU integration. With the clean coal gases produced through commercially available chemical processes, their compatibility as IGCC gas turbine fuel is investigated in the aspects the overall performance of the gas turbine system. The predictions by the present method show that the reduction of the air extraction from gas turbine to ASU results in a remarkable increase in the efficiency and net power of gas turbines, but it is accompanied with a shift of compressor operation point toward to surge limit. In addition, the present analysis results reveal the influence of compressor performance characteristics of gas turbine have to be carefully examined in designing the ASU integration process and evaluating the overall performance parameters of the gas turbine in IGCC Power plant.

• ETRI Journal
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• 제19권3호
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• pp.228-241
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• 1997

In this paper, we present a design of modem and vocoder digital signal processor (DSP) chips for CDMA mobile station. The modem chip integrates CDMA reverse link modulator, CDMA forward link demodulator and Viterbi decoder. This chip contains 89,000 gates and 29 kbit RAMs, and the chip size is $10 mm{\times}10.1 mm$ which is fabricated using a $0.8{\mu}m$ 2 metal CMOs technology. To carry out the system-level simulation, models of the base station modulator, the fading channel, the automatic gain control loop, and the microcontroller were developed and interfaced with a gate-level description of the modem application specific integrated circuit (ASIC). The Modem chip is now successfully working in the real CDMA mobile station on its first fab-out. A new DSP architecture was designed to implement the Qualcomm code exited linear prediction (QCELP) vocoder algorithm in an efficient way. The 16 bit vocoder DSP chip has an architecture which supports direct and immediate addressing modes in one instruction cycle, combined with a RISC-type instruction set. This turns out to be effective for the implementation of vocoder algorithm in terms of performance and power consumption. The implementation of QCELP algorithm in our DSP requires only 28 million instruction per second (MIPS) of computation and 290 mW of power consumption. The DSP chip contains 32,000 gates, 32K ($2k{\times}16\;bit$) RAM, and 240k ($10k{\times}24\;bit$) ROM. The die size is $8.7\;mm{\times}8.3\;mm$ and chip is fabricated using $0.8\;{\mu}m$ CMOS technology.

• Nuclear Engineering and Technology
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• 제53권4호
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• pp.1167-1175
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• 2021

The process of automation and monitoring in industrial control system involves the use of many types of sensors. A programmable logic controller plays an important role in the automation of the different processes in the power plant system. The major control units are boiler for temperature and pressure, turbine for speed of motor, generator for voltage, conveyer belt for fuel. The power plant units are controlled using microcontrollers and PLCs, but FPGA can be the feasible solution. The paper focused on the design and simulation of hardware chip to monitor boiler, turbine, generator and conveyer belt. The hardware chip of the plant is designed in Xilinx Vivado Simulator 17.4 software using VHDL programming. The methodology includes VHDL code design, simulation, verification and testing on Virtex-5 FPGA hardware. The system has four independent buzzers used to indicate the status of the boiler, generator, turbine motor and conveyer belt in on/off conditions respectively. The GSM is used to display corresponding message on the mobile to know the status of the device in on/off condition. The system is very much helpful for the industries working on plant automation with FPGA hardware integration.

• 한국수자원학회:학술대회논문집
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• 한국수자원학회 2022년도 학술발표회
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• pp.165-165
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• 2022

담수호는 하구에 방조제를 축조하여 인위적으로 조성된 저수지로, 배수갑문을 통해 적정수위를 유지하면서 이수 목적의 수자원으로 재활용할 경우 경제적이며 효율적인 수자원이 될 수 있다. 한편, 담수호는 유역의 최하류에 위치하므로 담수호의 통합적 수자원 관리를 위해서는 상류 유역 특성과 유입 오염물질 및 수체 특성에 대한 종합적인 이해를 바탕으로 수문, 수질, 염도 등 다양한수자원 요소를 고려하여 적절한 관리방안을 수립할 필요가 있다. 따라서 본 연구에서는 유역모형 및 호소모형을 연계하여 담수호의 내외 수위차를 고려한 배수갑문 운영 시나리오에 따른 호내 수문 및 수질 측면에서의 영향을 정량적으로 분석하였다. 충청남도 서산시에 위치한 간월호를 대상으로 HSPF (Hydrological Simulation Program-FORTRAN) 모형을 적용하여 상류유역의 장기유출량 및 수질 모의를 수행하여 호내 유입량 자료로 활용하였다. 호소 내 수리-수질 모의를 위해 3차원 수리해석 모형인 EFDC (Environmental Fluid Dynamics Code)와 호소수질모의 모형인 WASP (Water Quality Analysis Simulation Program)을 연계하여 배수갑문 운영에 따른 호내 수문 및 수질 변화를 모의하였다. 본 연구의 결과는 향후 수문 및 수질 영향을 고려한 담수호의 최적 수자원 관리방안 수립하는데 기초자료로 활용될 수 있을 것으로 기대된다.

• Nuclear Engineering and Technology
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• 제55권12호
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• pp.4382-4394
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• 2023

Passive auto-catalytic recombiners (PARs) are widely used to mitigate a hydrogen hazard. The first step to evaluate the hydrogen safety by PARs is to obtain qualified test data of the PARs for validation of their analytical model. SPARC PAR tests SP8 and SP9 were conducted to evaluate the hydrogen recombination characteristics of a honeycomb-shaped catalyst PAR. To obtain the hydrogen recombination rate from the PAR test data, two methods, Method-1 and Method-2, introduced by the THAI project, were applied. Since a large gradient of hydrogen concentration developed during hydrogen injection can cause a large error in the hydrogen mass obtained by integrating the measured hydrogen concentrations, a gate was installed at the PAR inlet to homogenize hydrogen in the test vessel before the PAR operation in the tests. A computational fluid dynamics (CFD) code with a PAR model was also applied to evaluate the characteristics of the PAR recombination according to the PAR inlet conditions, and the results were compared with those from Method-1 and Method-2. It was confirmed that the recombination rates from Method-1 require a correction factor to be compatible with results from Method-2 and the CFD simulation in the case of the SPARC-PAR tests.